Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2024/079816
Kind Code:
A1
Abstract:
A memory device in which, in a plan view, a plurality of pages are aligned in a column direction on a substrate and are formed by a plurality of memory cells aligned in a row direction, the memory device being characterized in that the memory cells included in each page have a semiconductor matrix, and at both ends of the semiconductor matrix, a first and second impurity layers, a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, and a channel semiconductor layer, the first impurity layer of the memory cell is connected to a source line and the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first selection gate line, the second gate conductor layer is connected to a plate line, the third gate conductor layer is connected to a second selection gate line, and at the completion of a page write operation and a page read operation, the voltage of the plate line is brought to a negative voltage less than 0V by capacitive coupling of the first and second selection gate lines to the plate line, thereby improving the data retention property of a write memory cell.
Inventors:
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/038066
Publication Date:
April 18, 2024
Filing Date:
October 12, 2022
Export Citation:
Assignee:
UNISANTIS ELECTRONICS SINGAPORE PTE LTD (SG)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
G11C16/04; G11C11/401; H10B12/00; H10B99/00
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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