Title:
LAYOUT METHOD FOR SCALABLE MULTI-DIE NETWORK-ON-CHIP FPGA ARCHITECTURE AND APPLICATION
Document Type and Number:
WIPO Patent Application WO/2024/077730
Kind Code:
A1
Abstract:
One technical solution of the present invention provides a layout method for a scalable multi-die network-on-chip FPGA architecture. The other technical solution of the present invention provides an application of the layout method for a scalable multi-die network-on-chip FPGA architecture. The present invention provides a scalable multi-die FPGA architecture based on a network-on-chip and a corresponding hierarchical recursive layout algorithm, and aims to directly map a register-transfer level dataflow design generated by means of existing high-level synthesis to the proposed interconnection architecture. According to the method provided by the present invention, the potential of a hierarchical topology can be explored, and special interconnection resources, such as a cross-grain line network, a network-on-chip and a high-speed transceiver, can be utilized more effectively.
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Inventors:
LUO JIANWEN (CN)
HA YAJUN (CN)
HA YAJUN (CN)
Application Number:
PCT/CN2022/134243
Publication Date:
April 18, 2024
Filing Date:
November 25, 2022
Export Citation:
Assignee:
UNIV SHANGHAI TECH (CN)
International Classes:
H01L25/065
Foreign References:
| US20220006733A1 | 2022-01-06 | |||
| US20220216156A1 | 2022-07-07 | |||
| CN115083466A | 2022-09-20 |
Other References:
LANG IAN; HUANG ZIQIANG; KAPRE NACHIKET: "Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs", 2020 IEEE 28TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), IEEE, 3 May 2020 (2020-05-03), pages 70 - 74, XP033779449, DOI: 10.1109/FCCM48280.2020.00019
Attorney, Agent or Firm:
SHANGHAI SHENHUI PATENT AGENT CO., LTD. (CN)
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