Title:
INTERMEDIATE CHIP, AND PROCESSING METHOD FOR CHIP STACKED PACKAGE
Document Type and Number:
WIPO Patent Application WO/2024/077811
Kind Code:
A1
Abstract:
Embodiments of the present disclosure provide an intermediate chip, and a processing method for a chip stacked package. The intermediate chip has a front surface and a back surface which are opposite to each other, the front surface of the intermediate chip is provided with first bumps, and the back surface of the intermediate chip is provided with second bumps. The intermediate chip provided by the present disclosure is provided with the first bumps on the front surface and the second bumps on the back surface, so that the intermediate chip can establish bump-to-bump connections with chips on both sides of the intermediate chip, the amount of solder at the connections between the intermediate chip and the chips on the both sides is increased, and solder offset is less likely to occur in the bump-to-bump connections. Thus, the defects such as cold soldering or failed soldering of bumps caused by chip warpage can be effectively reduced, the chip warpage control ability is improved, and the influence of chip warpage on the yield of package products is reduced.
Inventors:
LV KAIMIN (CN)
Application Number:
PCT/CN2023/073083
Publication Date:
April 18, 2024
Filing Date:
January 19, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/488; H01L21/60
Foreign References:
| US20120256322A1 | 2012-10-11 | |||
| CN104916552A | 2015-09-16 | |||
| CN114171505A | 2022-03-11 | |||
| CN113113397A | 2021-07-13 | |||
| JP2004327855A | 2004-11-18 | |||
| CN114400213A | 2022-04-26 | |||
| JP2012069903A | 2012-04-05 | |||
| CN103165479A | 2013-06-19 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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