Title:
INSTRUCTION-LEVEL PARALLEL SCHEDULING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2024/066875
Kind Code:
A1
Abstract:
Provided in the present application are an instruction-level parallel scheduling method and apparatus, an electronic device, and a storage medium. The instruction-level parallel scheduling method comprises: acquiring a DAG corresponding to an instruction set, and traversing the DAG to search in the instruction set intermediate operands corresponding to operation instructions having dependency relationship; according to the ready order of the intermediate operands, sorting the intermediate operands so as to obtain an intermediate operand list; generating an original DAG collectively corresponding to the intermediate operands, and, according to the arrangement priority level of the intermediate operand list, inserting in sequence the intermediate operands into the original DAG so as to obtain a target DAG; and according to the target DAG, performing parallel scheduling on the instructions in the instruction set.
Inventors:
LIU WEI (CN)
Application Number:
PCT/CN2023/115697
Publication Date:
April 04, 2024
Filing Date:
August 30, 2023
Export Citation:
Assignee:
SANECHIPS TECH CO LTD (CN)
International Classes:
G06F9/38
Foreign References:
| CN104424026A | 2015-03-18 | |||
| CN113296788A | 2021-08-24 | |||
| US20140082330A1 | 2014-03-20 |
Attorney, Agent or Firm:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS (CN)
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