The invention relates to a comparator with a reference voltage input and a difference voltage input together with an inverting output and a non-inverting output, wherein a switching threshold of the comparator may be predetermined by an upper threshold voltage and a lower threshold voltage with regard to the reference voltage.

Comparators of the generic type are known. These act as difference voltage transformers and are known to be used to convert analog voltage signals into digital signals.

Depending on the level of an input voltage superimposed over the reference voltage, the comparator switches at the output to a HIGH voltage level or a LOW voltage level. The reference voltage determines a threshold voltage, the output state being assumed to be HIGH when this is exceeded and LOW when it is fallen short of. To increase switching accuracy of the comparator, it is known to set an upper threshold voltage and a lower threshold voltage for the reference voltage (threshold voltage). The difference between the upper threshold voltage and the lower threshold voltage provides comparator hysteresis. The upper threshold voltage and the lower threshold voltage result in the fact that switching into the HIGH state requires the upper threshold voltage to be exceeded and switching into the LOW state requires the lower threshold voltage to be fallen short of. This hysteresis determined by the upper and lower threshold voltages ensures that the interference signal superimposed over the input signals does not have any effect on the switching state of the comparator.

Comparators provided with hysteresis are known for example from US-PS 5,617, 050, US-PS 5,798, 663, US-PS 5,610, 545, US-PS 5, 528, 185 and US-PS 6,166, 566. In these known comparators, in each case a constant upper threshold voltage and a constant lower threshold voltage are set, i. e. the difference between the upper threshold voltage and the reference voltage and between the reference voltage and the lower threshold voltage is identical.

It is an object of the invention to provide a comparator of the generic type which provides in a simple manner flexible adaptation to various applications.

This object is achieved according to the invention by a comparator having the features of claim 1. Because the upper threshold voltage and the lower threshold voltage may be set independently of one another, it is advantageously possible to set the difference

between the upper threshold voltage and the reference voltage and between the reference voltage and the lower threshold voltage to be asymmetric. In a preferred development of the invention, it is possible in particular to select the upper threshold voltage or the lower threshold voltage to be identical to the reference voltage and to design hysteresis thus only for the lower threshold voltage or for the upper threshold voltage. This opens up many and varied application options for the comparator according to the invention, especially that of triggering switchover when the reference voltage is exceeded or fallen short of, while input signal fluctuations may be suppressed either in the upper hysteresis range or the lower hysteresis range.

In a further preferred development of the invention, it is also possible to set the upper and lower threshold voltages, which may be set independently of one another, in each case at the level of the reference voltage. Thus, comparators may be obtained which operate as desired with hysteresis, optionally asymmetric hysteresis, or without hysteresis.

Thus, an optimal characteristic curve may be set for the comparator as a function of the application.

In a particularly preferred development of the invention, provision is made for setting of the upper threshold voltage and/or of the lower threshold voltage to be determined by modifying the channel width of p-channel transistors connected between the inverting output and the non-inverting output of the comparator. By modifying the ratio of the channel widths of the p-channel transistors relative to one another, it is possible simply to adjust the gain of the comparator and thus the hysteresis of the comparator symmetrically or asymmetrically.

It is additionally possible, in a preferred development of the invention, to adjust the channel widths of the p-channel transistors by a"metal-programmable"width or an "electrically programmable"width. In this way, the upper threshold voltage and/or the lower threshold voltage may be simply set independently of one another using methods known per se.

Further preferred developments of the invention are revealed by the other features mentioned in the subclaims.

The invention will be further described with reference to examples of embodiments shown in the drawings, to which, however, the invention is not restricted: Fig. 1 is a block diagram of a programmable comparator;

Figs. 2 and 3 show possible characteristic curves for the asymmetric comparator; Fig. 4 shows a first example of embodiment of a comparator according to the invention; Fig. 5 shows a second example of embodiment of a comparator according to the invention; Fig. 6 shows a third example of embodiment of a comparator according to the invention.

Fig. 1 is a block diagram of a comparator 100. A reference voltage VREF is present at an input INN. A voltage is applied to another input INP which results from superimposition of the reference voltage VREF and a differential input voltage VIN. The reference voltage VREF is constant, such that a HIGH voltage signal is obtained at an output OUTP if the differential input voltage VIN is positive and a LOW voltage signal is obtained at the output OUTP if the differential input voltage VIN is negative. The respectively inverted signals are applied to the output OUTN. The structure and mode of operation of such comparators 100 are known, such that these will not be explained in any more detail in the context of the description.

A first coupling element 12 is connected between the input INP and the output OUTP and a second coupling element 14 between the input INN and the output OUTN. The coupling elements 12 and 14 serve, in a manner still to be explained, in programming the hysteresis of the comparator 100. The coupling element 12 serves in setting an upper threshold voltage and the coupling element 14 in setting a lower threshold voltage of the comparator 100. The difference between upper threshold voltage and lower threshold voltage corresponds to the hysteresis of the comparator 100. The upper threshold voltage may be greater than/equal to the reference voltage VREF and the lower threshold voltage may be lower than/equal to the reference voltage V REF.

The operation of two embodiments of the comparator 100 is clear from the characteristic curves illustrated in Figs. 2 and 3. The differential input voltage V IN together with the HIGH voltage signal and LOW voltage signal present at the output OUTP are shown therein over the time t. The reference voltage V REF together with the upper threshold voltage ge V SO and the lower threshold voltage V SU are constant over time. The difference VSO-VSU corresponds to the hysteresis 16. According to the characteristic curves in Fig.

2, the differential input voltage VIN is smaller than the upper threshold voltage V SO in the period to to tl, such that the LOW voltage signal is present at the output OUTP. At the time tl, the differential input voltage VIN rises above the upper threshold voltage V SO, such that the comparator 100 switches to the HIGH voltage signal at the output OUTP. At the time t2, when the differential input voltage VIN falls below the lower threshold voltage VSU, the comparator switches back to the LOW voltage signal at the output OUTP. It is clear that an analog input voltage signal is converted into a digital signal. According to the illustration in Fig. 2, the hysteresis 16 is symmetric, i. e. the difference between upper threshold voltage VSO and reference voltage VREF matches the difference between the reference voltage VREF and the lower threshold voltage VISU.

In contrast thereto, in the case of the characteristic curves shown in Fig. 3, an asymmetric hysteresis 16 of the comparator 100 is programmed. The upper threshold voltage VSO here corresponds to the reference voltage VREF, such that the hysteresis 16 corresponds to the difference between the reference voltage VREF or upper threshold voltage VSO and the lower threshold voltage VSU. The output OUTP or OUTN is accordingly switched into the signal states HIGH or LOW in the event respectively of the upper threshold voltage V SO being exceeded or the lower threshold voltage V SU being fallen short of.

These characteristic curves shown in Figs. 2 and 3 are provided for clarification merely by way of example. Thus, other asymmetric hystereses 16 of the comparator 100 may also be programmed. For example, the lower threshold voltage VSU may coincide with the reference voltage VREF, while the upper threshold voltage V SO is greater than the reference voltage VREF. Furthermore, the comparator 100 may be designed with different voltage differences between the upper threshold voltage VSO and the reference voltage VREF and the reference voltage VREF and the lower threshold voltage VSU.

The nub of the invention is to design the comparator 100 and its coupling elements 12 and 14 in such a way that the hysteresis 16 may be freely programmed, in particular asymmetrically programmed, i. e. the upper threshold voltage V SO and the lower threshold voltage V SU may be set independently of one another.

Fig. 4,5 and 6 show various circuit arrangements for the comparator 100, which allow mutually independent setting of the upper threshold voltage V SO and the lower threshold voltage VISU.

It is clear from the circuit arrangement 10 shown in Fig. 4 that it is possible to go beyond a generally known standard construction of the comparator 100 with the n-channel transistors M1 and M4 and the p-channel transistors M2 and M5 by additionally connecting p-channel transistors M3 and M6. The p-channel transistor M6 constitutes the coupling element 12 and the p-channel transistor M3 the coupling element 14 (Fig. 1).

All the p-channel transistors M2, M3, M5 and M6 have the same channel length LP and all the n-channel transistors M1 and M4 have the same channel length LN. In addition, the p-channel transistors M2 and M5 have the same channel width WP and the n- channel transistors Ml and M4 have the same channel width WN.

It is clear from this that the switching behavior of the circuit arrangement 10 may be set solely by selecting the channel widths W6 of the p-channel transistor M6 or W3 of the p-channel transistor M3. The following applies to the width ratios: k3 = W3/WP and k6 = W6/WP.

If a symmetric hysteresis 16 is initially assumed, the following applies: k3 = k6 = k.

From this, the following is obtained for the gain of the comparator 100: wherein ßsqP and (3sqN are the transconductance parameters of the p-channel and n-channel transistors respectively with a ratio of the channel dimensions (channel width to channel length) of W/L = 1. From this, it is clear that the gain of the comparator 100 may be adjusted via the factor k. According to the circuit arrangement 10 in Fig. 4 the following applies: k < 1-comparator 100 with finite gain ; k = 1-comparator 100 with maximum gain and k > 1-comparator 100 with symmetric hysteresis 16.

It is clear that, by selecting the width ratios k3 or k6, the size of the hysteresis 16 and the position of the upper threshold voltage VSO or of the lower threshold voltage V SU respectively may be adjusted independently of one another relative to the reference voltage VREF.

If the comparator 100 is to be operated with hysteresis 16, the upper threshold voltage VSO is obtained as follows:

It is clear that the upper threshold voltage VSO is positive for k6 > 1 and zero for k6 = 1.

Similarly, the following is obtained for the lower threshold voltage VSU : It is clear that the lower threshold voltage VSU is negative for k3 > 1 and zero for k3 = 1.

On the basis of these relationships, the difference VSO-VSU may be determined for the hysteresis 16, wherein the following applies: 2 * LN 8 I BLAS ß sqrt (k6)-1 1-sqrt (k3)) TT z td ytt | * _. l3sqN * WN sqrt (l + k6) sqrt (l + k3) These equations apply for the assumption k3 > 1 and k6 1.

On the basis of the above-mentioned relationships, it is clear that comparators 100 with a hysteresis 16 or without hysteresis 16 may be obtained as a function of the width ratios k3 and k6. By mutually independent adjustment of the width ratios k3 > 1 and k6 2 1, the upper threshold voltage VSO and the lower threshold voltage VSU may be adjusted independently of one another. If the width ratios k3 and k6 are of equal size, a comparator 100 is obtained with symmetric hysteresis 16. If the width ratios k3 and k6 are different, an asymmetric hysteresis 16 is obtained with regard to the reference voltage VREF.

It is also possible to position the upper threshold voltage V SO or the lower threshold voltage VSU on the reference voltage VREF (c. f. in this respect also Fig. 3) by adjusting the width ratio k6 = 1 or the width ratio k3 = 1.

The width ratios k3 and/or k6 may also be set slightly greater than 1, for example k3 and/or k6 = 1.01, such that fine adjustment of the comparator 100 to the reference voltage V REF may be achieved.

If the comparator 100 is set without hysteresis 16, i. e. the width ratios k3 and k6 are equal to k, wherein k < 1, the gain of the comparator 100 may be simply adjusted within a wide range. Where k3 = k6 = 1, the greatest possible gain is achieved. This is the point of transition to the comparator 100 with hysteresis 16. For the upper threshold voltage V SO and the lower threshold voltage VSU, the result, according to the above-mentioned relationships (where k3 = k6 = 1), is 0 Volt, i. e. the switchover point of the comparator 100 is at the reference voltage V REF. The hysteresis 16 is thus zero.

Adjustment of the width ratios k3 and k6 for programming the hysteresis 16 may be achieved in various possible ways. On the one hand, there is the possibility of

providing, on integration of the circuit arrangement 10, a fixed channel width W3 for the transistor M3 and a fixed channel width W6 for the transistor M6.

Another possibility is obtained in that, by changing a metal mask of the transistors M3 and M6 after integration thereof into the circuit arrangement 10, the latter may be adapted subsequently to a desired hysteresis 16. For this purpose, a"metal-programmable" channel width may be set for the transistors M3 and M6.

Finally, through electrical programming of the integrated circuit arrangement 10, the hysteresis 16 may be dynamically adapted to various instances of application of the comparator 100. This"electrically programmable"channel width may thus be set for the transistors M3 and M6. Both the setting of metal-programmable and of electrically programmable channel widths are generally known, such that they will not be explained in any more detail in the context of the present description.

Fig. 5 shows a modified embodiment of the circuit arrangement 10 according to Fig. 4. In the case of the circuit arrangement 10 according to Fig. 4, the voltage level at the output OUTP or at the inverting output OUTN in the HIGH state may assume the value of the supply voltage VDD. However, in the LOW switching state, the voltage potential 0 Volt cannot be achieved. This may be desirable in the case of various application options for the comparator 100, in particular with subsequent digital circuits. According to Fig. 5, it is therefore proposed to connect the output OUTP with a further p-channel transistor M7, which is connected with a further current source I BIAS2. In this way, the possibility is obtained, in addition to logical inversion of the output signal OUTP into OUTN, of setting the LOW voltage signal at the value 0 Volt.

Finally, Fig. 6 shows a further embodiment of the circuit arrangement 10, in which the p-channel transistors M3 and M6 are each subdivided into parallel-connected p- channel transistors M31 and M32 and M61 and M62 respectively. The p-channel transistor M32 may be connected via a switching means S3 to the supply voltage VDD and the p- channel transistor M62 via a switching means S6 to the supply voltage VDD. In this way, it is possible to program the channel width W3 or W6 of the transistors M3 or M6 respectively by actuating the switching means S3 and/or S6. This programming could be refined by subdividing the p-channel transistors M3 or M6 into more than two parallel-connected p- channel transistors, of which at least two would be connected to the supply voltage VDD via corresponding switching means S. Depending on actuation of the switching means, various setting options for the hysteresis 16 are then obtained, which, as explained, may also be asymmetric.

LIST OF REFERENCE NUMERALS 100 Comparator INP Input 10 Circuit arrangement INN Input 12 First coupling element OUTP Output 14 Second coupling element OUTN Output 16 Hysteresis HIGH Signal state LOW Signal state t Time VREF Reference voltage VIN Differential input voltage V SU Lower threshold voltage VSO Upper threshold voltage IBIAS Current source VDD Supply voltage WP Channel width of the p-channel transistors WN Channel width of the n-channel transistors LP Channel length of the p-channel transistors LN Channel length of the n-channel transistors M1 n-channel transistor M2 p-channel transistor M3 p-channel transistor M4 n-channel transistor M5 p-channel transistor M6 p-channel transistor M31 p-channel transistor (split) M32 p-channel transistor (split) M61 p-channel transistor (split) M62 p-channel transistor (split)