SENSOR SYSTEM FOR SPARSE SENSING OF ELECTROCHEMICAL CELLS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of priority of US Provisional

Application No. 63/420,426 filed October 28, 2022, entitled “ELECTROCHEMICAL SYSTEMS WITH MASSIVELY PARALLEL ARRAY OF CONTROLLABLE ELECTROCHEMICAL CELLS AND SENSOR SYSTEM FOR SPARSE SENSING OF ELECTROCHEMICAL CELLS,” the entire contents of which is incorporated by reference herein.

GOVERNMENT SUPPORT

[0002] This invention was made with government support under 2019-19081900002 awarded by Intelligence Advanced Research Projects Activity (IARPA) and under 2025158 awarded by the National Science Foundation (NSF). The government has certain rights in the invention.

FIELD

[0003] The present disclosure generally relates to apparatuses and methods for performing, in sequence or in parallel, a plurality of electrochemical reactions and measuring, in sequence or in parallel, electrical signals arising from the electrochemical reactions, to monitor and control local chemical characteristics of a plurality of environments of the reactions and provide chemically diverse sources for use in screening for biological activity and/or chemical activity. The apparatuses may be scalable and may be used for massively parallel operations, such that at least ten thousand, or tens of thousands, or at least one hundred thousand, or hundreds of thousands, or at least a million electrochemical reactions may be performed.

BACKGROUND

[0004] Molecular reactions may be used in a wide variety of applications, such as to screen for biological activity and to prepare chemical libraries. In some instances, these reactions may be manipulated electrochemically, enabling localized control of individual reaction sites via controlled application of electrical signals. Progress of the electrochemical reactions may be observed by monitoring the sites for changes. In some cases, in order to perform multiple electrochemical reactions for a statistically reliable assessment, an array of reaction sites may be used to perform electrochemical reactions in parallel. An increase in the number of reaction sites, however, also may increase the complexity of controlling the electrochemical reactions (e.g., to ensure uniform and/or precise/accurate conditions), and also may increase the complexity of monitoring the sites.

SUMMARY OF THE DISCLOSURE

[0005] Electrochemical systems and methods that include a large number of electrical stimulation sites, which may be controlled individually, or collectively, or in groups, may provide flexibility in performing a plurality of different processes simultaneously or performing a single process many times. The former may be advantageous for investigations where, e.g., optimal stimulation parameters have not yet been determined, whereas the latter may be advantageous for producing a large number of reactant products via the large number of stimulation sites. In some implementations of the present technology, an electrochemical system may include integrated circuits based on complimentary metal-oxide- semiconductor (CMOS) technology, and also may include a microelectrode array that has individually addressable electrode cells, or “pixels.” Some or all of the pixels may each comprise a pair of anode and cathode electrodes for localized stimulation, as well as one or more bits of integrated digital memory for individually addressed programming. In some implementations of the disclosed technology, a chip comprising an array of pixels and on- chip circuitry for both stimulation and sensing of the pixels may have an architecture such that a pixel “fill-factor,” or area of the chip occupied by active pixel circuits, is over 90% of a total area of the chip. In some implementations of the disclosed technology, some or all of the pixels may each include a pixel circuit able to perform a uniform initialization, such that all electrode surfaces of an individual pixel, or a group of pixels of the array, or all pixels of the array may be initialized or swept with an initialization voltage via cyclic voltammetry. For stimulation modalities, the pixel circuits may advantageously reduce a leakage current when the pixel is OFF, and may advantageously reduce current consumption by 50% when the pixel is ON. For sensing modalities, pixels at specific locations in the array may be designated for monitoring via one or more patterned layers of material formed during a postfabrication stage of the chip, which may advantageously provide freedom in configuring an arrangement of electrochemical sites to be monitored. In some implementations of the disclosed technology, the architecture of the chip may be scalable to have a multi-well form factor, and may be realized by wafer-scale processing for electrochemical systems able to perform massively parallel operations. For example, a total number of operations, which may be performed in parallel, or in parallel groups, or consecutively, may be in a range from hundreds of thousands to several million, although smaller numbers also are possible. Optionally, the chip may be provided with one or more on-chip temperature sensors to measure, e.g., a temperature of the silicon die during an electrochemical reaction.

[0006] According to an aspect of the technology of the present disclosure, an electrochemical system is provided. The system may comprise: a multi-chip apparatus comprising a plurality of chips; and a host system configured to provide host signals for controlling the chips and to receive readout signals based on electrical values detected at the chips. The multi-chip apparatus may be configured such that at least one chip is in electrical communication with one or more adjacent chips of the multi-chip apparatus, at least one chip comprises: an array of pixels, and chip circuitry configured to provide stimulation currents to the pixels, to sense open-circuit voltages (OCVs) of at least some of the pixels, and to output readout signals to the host system as part of the readout signals received by the host system. [0007] In some embodiments of this aspect, the chip circuitry may comprise: stimulator circuitry configured to provide the stimulation currents to the array (4), to cause stimulation of a group of at least some of the pixels, and sensor circuitry configured to sense the OCVs of the group of pixels, such than an OCV of an individual pixel of the group of pixels may be sensed and output as a readout signal to the host system and/or OCVs of the group of pixels may be sensed and output at least one readout signal to the host computer. The sensor circuitry may be configured to sense the OCVs of the group of pixels while the group of pixels are being stimulated. A total number of pixels in the array may be in a range of: 100,000 pixels to 500,000 pixels, or 500,000 pixels to 1,000,000 pixels, or 250,000 pixels to 750,000 pixels, or 750,000 pixels to 1,250,000 pixels. Two or more chips of the multi-chip apparatus may share a common semiconductor substrate.

[0008] In some embodiments of this aspect, the host system may comprise: a host computer comprising at least one microprocessor and at least one memory, a field programmable gate array (FPGA) or microcontroller, and an analog-to-digital converter (ADC). The FPGA or microcontroller may be configured to receive host signals provided by the host computer and to output control signals to the chip circuitries of the multi-chip apparatus based on the host signals, as well as to transmit recorded OCV or other relevant experimental data to the host computer. The ADC may be configured to receive and digitize the readout signals from the chip circuitries and to output digitized readout signals to the FPGA.

[0009] In some embodiments of this aspect, the chips of the multi-chip apparatus may be arranged in a plurality of chip columns and a plurality of chip rows. The multi-chip apparatus may comprise: a plurality of column interconnection circuits each connecting adjacent chips in a column direction, and a plurality of row interconnection circuits each connecting adjacent chips in a row direction. Two or more of the column interconnection circuits may be column repeaters configured to receive control signals and/or to transmit control signals in the column direction. Two or more of the row interconnection circuits may be repeaters configured to receive control signals and/or to transmit control signals in the row direction. In some embodiments, the row and column interconnection circuits may connect multiple chips directly via bond wires, via a multi-die interposer, or via wireless board-to- board connections over a network.

[0010] In some embodiments of this aspect, the pixels of the array may be arranged in a plurality of pixel columns and a plurality of pixel rows. The chip circuitry may comprise: a clock generator configured to receive an input clock signal from the host system and to output a plurality of non-overlapping clock signals based on the input clock signal, and a plurality of buffers configured to buffer the non-overlapping clock signals. Each buffer may be operatively connected to pixels of a corresponding pixel column or a corresponding pixel row of the array such that the non-overlapping clock signals in the buffer are usable to control a pixel stimulation process in the pixels of the corresponding pixel column or the correspond pixel row of the array.

[0011] In some embodiments, the chip circuitry may comprise: a plurality of first circuitry regions configured to communicate with columns of pixels of the array, a plurality of second circuitry regions configured to communicate with rows of pixels of the array, and a plurality of third circuitry regions configured to sense the OCVs at the pixels of the array and to output the readout signals to the host system. The first, second and third circuitry regions may be located at a first perimeter region of the chip such that the array is surrounded by the first, second, and third circuitry regions. An area of the array may be at least 90% of a total area of the chip.

[0012] In some embodiments, the first circuitry regions may comprise: a plurality of column drivers respectively corresponding to pixel columns of the array, and a plurality of column shift registers respectively corresponding to the pixel columns of the array. The second circuitry regions may comprise: a plurality of row drivers respectively corresponding to pixel rows of the array, and a plurality of row shift registers respectively corresponding to the pixel rows of the array. Some or all of the third circuitry regions may each comprise: a plurality of chip amplifiers configured to buffer OCVs sensed from the pixels of the array, and a multiplexer configured to measure the buffered OCVs individually from one or more selected pixels of the array and to output measured voltages as a readout signal. The chip circuitry may comprise a configuration memory configured to store a stimulation configuration for pixels of the array. For some or all of the pixels of the array, each pixel may be individually addressable such that the pixel may be stimulated with a stimulation current for the pixel and such that an OCV of the pixel may be sensed during stimulation. [0013] In some embodiments, the chip may comprise: a pad ring and at least one routing gutter rings. The pad ring may be located at a first periphery of the chip. The pad ring may comprise a plurality of contact pads through which electrical power and electrical signals may be provided to the chip and through which output signals may be provided from the chip. The at least one routing gutter ring may be configured to route the electrical power and the electrical signals from the pad ring to the first, second, and third circuitry regions and to communicate signals amongst the first, second, and third circuitry regions and amongst the pixels of the array and the first, second, and third circuitry regions via routing gutters. A portion of the routing gutter ring may surround the array.

[0014] In some embodiments, the chip may comprise four quadrants, some or all of the quadrants may each include: a subarray of the pixels of the array and one of the third circuitry regions. For some or all of the quadrants, the chip amplifiers of the quadrant may be configured to buffer OCVs sensed from the pixels of the subarray of the quadrant, and the multiplexer of the quadrant may be configured to measure the buffered OCVs individually from one or more selected pixels of the subarray of the quadrant and to output measured voltages as readout signals.

[0015] In some embodiments of this aspect, the array may comprise an array of electrode arrangements overlaying an array of pixel circuits. The pixel circuits may be operatively connected to the electrode arrangements such that, for at least some of the pixels of the array, each pixel may comprise an electrode arrangement overlaying a pixel circuit. The electrode arrangement may comprise a plurality of electrodes arranged on an electrode level of the array. The pixel circuit may be configured to electrically connect to the electrodes and may be arranged on a pixel-circuitry level of the array. The electrodes may include: a first stimulation electrode, a second stimulation electrode, and a sensing electrode. The first and second stimulation electrodes may be arranged as concentric rings and may have a common region. The sensing electrode may be located within the common region. The first and second stimulation electrodes may be connected to the stimulator circuitry, and the sensing electrode may be connected to the sensor circuitry. The pixel circuit may be configured to provide, selectively, a cathode stimulation current to the first stimulation electrode or an anode stimulation current to the second stimulation electrode.

[0016] In some embodiments, the pixel circuit may comprise: a first current stimulator configured to provide a first stimulation current to the first stimulation, a second current stimulator configured to provide a second stimulation current to the second stimulation electrode, and a plurality of switches configured to permit the first stimulation current to be provided to the first stimulation electrode or the second stimulation current to be provided to the second stimulation electrode based on the non-overlapping clock signals and signals from an in-pixel memory of the pixel circuit. The in-pixel memory may be configured to store configuration bits for enabling connection of the first current stimulator to the first stimulation electrode or the second current stimulator to the second stimulation electrode.

[0017] In some embodiments of this aspect, the chip may include an insulative pixelmonitoring layer configured to permit an OCV of at least one pixel of a group of monitored pixels of the array to be contacted through pixel-contact openings in the pixel-monitoring layer. The chip may include a plurality of wirings configured to contact one or more of the electrodes of at least one of the monitored pixels, via the pixel-contact openings, to permit the OCVs of the monitored pixels to be detected.

[0018] In some embodiments, the chip may comprise four quadrants. Some or all of the quadrants may each comprise: a subarray of the pixels of the array, and a quadrant block. The quadrant block may comprise: amplifiers configured to buffer OCVs sensed from at least the monitored pixels of the subarray of the quadrant, and a multiplexer configured to measure the buffered OCVs individually from at least the monitored pixels of the subarray of the quadrant and to output measured voltages as readout signals. The pixels of the array may be arranged in a plurality of pixel columns, and some or all of the pixel columns may each comprise at least one of one of the monitored pixels. In some embodiments, some or all of the pixel columns may each comprise two of the monitored pixels and two of the wirings respectively configured to contact the two of the monitored pixels.

[0019] In some embodiments, the first current stimulator may be a cathode stimulator and may comprise a first switched capacitor controlled by first and second cathode clock signals from the clock generator. The second current stimulator may be an anode stimulator and may comprise a second switched capacitor controlled by first and second anode clock signals from the clock generator. The first and second cathode clock signals and the first and second anode clock signals may be non-overlapping clock signals. The pixel circuit may include a switch system comprising: cleaning switches and leakage-compensation switches. The cleaning switches may be configured to clean the first and second stimulation electrodes. The cleaning switches may allow a cleaning voltage (Vciean) to be applied to the first and second stimulation electrodes based on a cleaning control signal (Clean_en) provided by the host system. The leakage-compensation switches may be configured to control a leakage current at the first and second stimulation electrodes. The cleaning control signal may cause the first and second stimulation electrodes to be swept with the cleaning voltage by a cyclic voltammetry process. In some embodiments, for at least some of the pixels of the array, the cleaning control signal and the configuration bits stored in the pixel memories of the pixels may control the switch systems of the pixels to perform a cyclic voltammetry process to initialize the first and second stimulation electrodes of the pixels uniformly, such that the first and second stimulation electrodes of the pixels may be uniformly at a common voltage. In some embodiments, for a pixel that is not to be stimulated with a stimulation current during an electrochemical process, the configuration bits stored in the pixel memory of the pixel may control the switch system of the pixel such that: the leakage-compensation switches may be in an open state, the cleaning switches may be in a closed state to permit the cleaning voltage to be applied to first and second stimulation electrodes, and the cleaning voltage may be set to a reference voltage of a solution of the electrochemical process. In some embodiments, the switch system may comprise first and second output switches, and the configuration bits stored in the pixel memory may control the switch system such that switchenable control signals are provided to the leakage-compensation switches and the first and second output switches to: provide a cathode stimulation current to the first stimulation electrode or provide the anode stimulation current to the second stimulation electrode. In some embodiments, the first current stimulator may comprise a first bias-control transistor configured to selectively permit a first bias current to charge the first switched capacitor when the first switched capacitor is switched on, and the second current stimulator may comprise a second bias-control transistor configured to selectively allow a second bias current to charge the second switched capacitor when the second switched capacitor is switched on.

[0020] According to another aspect of the technology of the present disclosure, an electrochemical chip apparatus is provided. The apparatus may comprise at least one chip, which may comprise: an array of pixels, and chip circuitry configured to provide stimulation currents to the pixels, to sense open-circuit voltages (OCVs) of at least some of the pixels, and to output readout signals to an off-chip device. The chip circuitry may comprise: stimulator circuitry configured to provide the stimulation currents to the array, to cause stimulation of a group of at least some of the pixels, and sensor circuitry configured to sense the OCVs of the group of pixels, such than OCVs of individual pixels of the group of pixels may be sensed and output as the readout signals. The pixels of the array may be arranged in a plurality of pixel columns and a plurality of pixel rows. The chip circuitry may comprise: a clock generator configured to output a plurality of non-overlapping clock signals, and a plurality of buffers configured to buffer the non-overlapping clock signals. Each buffer may be operatively connected to pixels of a corresponding pixel column or a corresponding pixel row of the array such that the non-overlapping clock signals in the buffer are usable to control a pixel stimulation process in the pixels of the corresponding pixel column or the correspond pixel row of the array.

[0021] In some embodiments of this aspect, the chip circuitry may comprise: a plurality of first circuitry regions configured to communicate with columns of pixels of the array, a plurality of second circuitry regions configured to communicate with rows of pixels of the array, and a plurality of third circuitry regions configured to sense the OCVs at the pixels of the array and to output the readout signals. The first, second and third circuitry regions may be located at a first perimeter region of the chip such that the array may be surrounded by the first, second, and third circuitry regions.

[0022] In some embodiments, the array may be similar to the array described above for the electrochemical system.

[0023] In some embodiments, the chip circuitry may be similar to the chip circuitry described above for the electrochemical system.

[0024] In some embodiments, the chip may be similar to the chip described above for the electrochemical system.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A skilled artisan will understand that the accompanying drawings are for illustration purposes only. It is to be understood that in some instances various aspects of the present disclosure may be shown exaggerated or enlarged to facilitate an understanding of the disclosure. In the drawings, like reference characters generally refer to like features, which may be functionally similar and/or structurally similar elements, throughout the various figures. The drawings are not necessarily to scale, as emphasis is instead placed on illustrating and teaching principles of the various aspects of the present technology. The drawings are not intended to limit the scope of the claims or the present disclosure in any way. In the drawings:

[0026] FIG. 1 schematically depicts a block diagram of an electrochemical system, according to some embodiments of the present technology;

[0027] FIG. 2A schematically depicts a chip comprised of an array of pixels, according to some embodiments of the present technology;

[0028] FIG. 2B schematically depicts a chip comprised of circuitry located at a periphery surrounding an array of pixels, according to some embodiments of the present technology;

[0029] FIG. 3 schematically depicts block diagram of an electrochemical system, according to some embodiments of the present technology;

[0030] FIG. 4A schematically depicts a top perspective view of a pixel, according to some embodiments of the present technology;

[0031] FIG. 4B schematically depicts an electrode structure of a pixel, according to some embodiments of the present technology;

[0032] FIG. 5 schematically depicts a scalable chip architecture for a chip of an electrochemical apparatus, according to some embodiments of the present technology;

[0033] FIG. 6 schematically depicts a plurality of chips forming a multi-chip structure, according to some embodiments of the present technology;

[0034] FIG. 7 shows a diagram of a pixel circuit, according to some embodiments of the present technology;

[0035] FIG. 8 schematically depicts a diagram of a pixel circuit and a clock generator in relation to electrodes of a pixel, according to some embodiments of the present technology;

[0036] FIG. 9 schematically depicts a cross section of an electrochemical flow-cell apparatus, according to some embodiments of the present technology;

[0037] FIGs. 10A and 10B schematically depict a cross section and a top perspective view, respectively, of an electrochemical flow-cell apparatus, according to some embodiments of the present technology; and

[0038] FIG. 11 schematically depicts an arrangement for performing sparse sensing of a subset of pixels of a pixel array, according to some embodiments of the present technology; and

[0039] FIG. 12 schematically depicts a cross section of a chip configured for sparse sensing, according to some embodiments of the present technology. DETAILED DESCRIPTION

[0040] The inventors have recognized and appreciated a need for spatially organized, programmatic molecular synthesis reactions, e.g., to provide chemically diverse sources for use in screening for biological activity, to prepare chemical libraries, etc. In some instances, these reactions may be manipulated electrochemically and may allow localized control of individual synthesis sites or groups of synthesis sites via electrical control signals specifically provided to the individual sites or groups of sites. The inventors also have recognized and appreciated that an ability to monitor progress of these reactions as they occur may be desirable.

[0041] Microelectrode arrays (MEAs) based on CMOS technology have become a standard platform for cellular investigation of electrogenic cells with electrical stimulation and recording of sensed signals and have been used commercially for electrochemical synthesis of custom DNA oligos. In some conventional MEA systems, active electrode arrays are used to generate reactions that occur at an electrode-electrolyte interface, when a voltage or a current is applied to desired electrodes. Some conventional MEA systems use a voltage stimulation scheme because a stimulation voltage can be easily shared amongst multiple stimulation sites and selectively applied via an on-chip switch network. However, voltage stimulation typically maintains a potential or voltage of a pair of electrodes rather than a reaction-dependent charge, and therefore voltage stimulation may not be desirable for some applications. Instead, current stimulation may be preferred for some applications because current stimulation may allow quantitative control of an electrochemical reaction rate. This quantitative control of redox reactions may provide a higher degree of reaction-rate control accuracy, which may result in reliable and reproducible localized control of individual synthesis sites, compared with voltage stimulation. The inventors have recognized and appreciated that for current stimulation, a stimulation current may not be evenly distributed across an array of reaction sites and may depend on an impedance of a location where the stimulation current is shared. Accordingly, the inventors have recognized and appreciated a desire for each electrode of a reaction site to have an individual current-based stimulator.

Otherwise, only electrodes that are directly connected to a current source can be concurrently stimulated with current at any given time, thereby precluding simultaneously initiated and continuous current stimulation at an array level. The inventors have recognized and appreciated that through use of a measured current to determine a charge flow of an electrochemical reaction, the reaction may be quantified in terms of a number of charged species participating in the reaction.

[0042] A multifunctional architecture for a CMOS chip is disclosed herein that efficiently utilizes a die area of the chip for the chip’s array of pixels. The chip is configured such that anode/cathode electrode pairs of the pixels may be stimulated with independent current values at an array level. An open circuit voltage (OCV) may be measured or sensed at a sensing electrode of each pixel of the array or sensing electrodes of selected pixels of the array. The OCV may be measured or sensed at the sensing electrodes of the pixels during stimulation of the anode/cathode electrode pairs of the pixels.

[0043] As noted above and elsewhere herein, to accommodate an array with as many pixels as possible in a chip’s die area, on-chip hardware or circuitry for stimulation and for sensing of the pixels is optimized for peripheral regions surrounding the array. In some embodiments of the disclosed technology, a pixel fill factor of over 90% may be achieved (see, e.g., FIG. 2B). In some embodiments, for stimulation, non-overlapping clock signals may be generated on-chip and may be buffered and provided to pixels across the array, and a stimulation pattern of the pixels may be programmed using on-chip shift registers operating in conjunction with the non-overlapping clock signals. In some embodiments of the technology disclosed herein, the shift registers and clock generators for generating the nonoverlapping clock signals may be disposed in the peripheral regions and may be aligned column-wise and row-wise with columns and rows of the array. In some embodiments, each pixel may include a pixel circuit located under the pixel’s electrode arrangement, i.e., the pixel’s anode, cathode, and sensing electrodes (see FIG. 4A), such that the array of pixels may comprise an array of electrode assemblies overlaying an array of pixel circuits. The pixel circuits may be configured to stimulate respective anode/cathode electrode pairs with controllable current using shared bias voltages and clock signals. In some embodiments, for sensing, amplifiers may be provided in each corner block of a quadrant of the chip to buffer an OCV from each sensing electrode of pixels of the quadrant, for pre-designated pixels of the quadrant or for all pixels of the quadrant. Each comer block may include a multiplexer to select or read out, one by one, the OCVs buffered by the amplifiers, such that the multiplexer may measure the OCV at each sensing electrode in a time-division multiplexed manner. In some embodiments, analog circuits of the on-chip circuitry may be located at the comer blocks of the chips. The analog circuits may include the amplifiers the multiplexers, and reference current generators. By confining the on-chip circuitry to the peripheral regions surrounding the array, the area of the chip used by the on-chip circuitry may be minimized to realize a chip having an array of 1,000,000 pixels (“IM chip”) or more, with each pixel being configured to provide a micro-site for an individual electrochemical reaction. In some embodiments, off-chip hardware that may be used in conjunction with the on-chip circuitry may include at least one analog-to-digital converter (ADC) configured to, e.g., convert analog representations of OCVs into corresponding digital values, and a field-programmable gate array (FPGA) configured to receive the digital values of the OCVs and to transfer the digital values of the OCVs to a host system for further processing (see FIG. 3). The host system may comprise at least one computer processor and at least one memory.

[0044] According to some embodiments of the technology disclosed herein, each pixel may include an electrode arrangement comprising anode and cathode electrodes for electrochemical stimulation and a sensing electrode, thus enabling both concurrent stimulation and monitoring to be performed simultaneously at a pixel level. In some embodiments, the electrode arrangement may comprise a pair of concentric, ring-shaped anode and cathode electrodes and a sensing electrode located at a central region within the ring-shaped anode and cathode electrodes (see FIG. 4B). The anode and cathode electrodes may be configured to manipulate localization of electrochemical reagents with a desired reaction rate by accurately controlling an anodic current or a cathodic current. The sensing electrode may be configured to measure an OCV at the central region. Therefore, as noted above, individual monitoring of an OCV of each pixel may be performed simultaneously with an electrochemical reaction, thus enabling a progress of the electrochemical reaction to be monitored for each pixel in situ, i.e., during stimulation. In some embodiments, electrical monitoring via the sensing electrodes may allow an electrochemical reaction procedure to be streamlined and automated by, e.g., providing an all-electrical chip-scale interface controlled by a computer processor.

[0045] According to some embodiments of the technology disclosed herein, for each pixel circuit, electrode stimulation may be applied when an enable signal for stimulation En is asserted (see FIG. 8). A current stimulator of the pixel circuit may be based on a switched capacitor, such that adjustment of an average value of an injection current may be accomplished by adjusting a frequency of a clock signal $ and/or by adjusting a magnitude of bias voltages VN and Vp applied to the current stimulator. A global clock generator may provide non-overlapping clocks signals $i _a , $2a, $ic, $2c, which may be buffered column-by- column to the array of pixels. As noted above and elsewhere herein, the pixel circuits may be located directly under the electrode assemblies, this minimizing routing lines connecting each pixel circuit to its corresponding electrode arrangement. This may advantageously permit a greater area of the chip to be used for pixels instead of for on-chip circuitry and routing interconnects.

[0046] Turning now to the figures, FIG. 1 schematically depicts a block diagram of an electrochemical system 1000, according to some embodiments of the present technology. The system 1000 may comprise an electrochemical cell 1002 operatively coupled to a processing system 1006 (e.g., a computer system). The electrochemical cell 1002 may comprise a semiconductor substrate 1003 supporting a first electrode 110, a second electrode 120, and a third electrode 130. In some embodiments, the electrodes 110, 120, 130 may be disposed on a surface 1003a of the semiconductor substrate 1003. In some embodiments, the electrochemical cell 1002 may be in an electrochemical reagent solution 1004 comprised of species that may participate in an electrochemical reaction, such as a redox reaction. The first electrode 110 may be a cathode electrode, where an electron is donated in a reduction portion of an electrochemical reaction. The second electrode 120 may be an anode electrode, where an electron is accepted in an oxidation portion of the electrochemical reaction. The third electrode 130 may be a sensing electrode and may be used to sense an OCV of the electrochemical reaction. The processing system 1006 may provide signals (e.g., control signals) to the electrochemical cell 1002 and receive signals (e.g., detected voltage and/or current signals) from the electrochemical cell 1002. In some embodiments, the electrochemical cell 1002 may correspond to a pixel of the system 1000. In some embodiments, the electrochemical cell 1002 may be fabricated with CMOS techniques known in the art of semiconductor processing. It should be understood, however, that fabrication techniques other than CMOS fabrication techniques may be used instead of or in addition to CMOS fabrication techniques to form various electronic components discussed herein.

[0047] According to some embodiments of the present technology, the semiconductor substrate 1003 may comprise electronic circuitry formed in and/or on the substrate 1003. In some embodiments, the electronic circuitry may include CMOS electronics 1005 configured to drive the cathode and anode electrodes 110, 120 with voltage stimulation or current stimulation. For example, the CMOS electronics 1005 may include voltage sources and/or current sources configured to drive the anode and cathode electrodes 120, 110 with positive and negative polarities, respectively. In some embodiments, corresponding oxidation and reduction reactions near the electrodes 110, 120 may be manipulated using an applied voltage and/or an applied current. Progress of the reactions may be monitored by monitoring an OCV at the sensing electrode 130. In some embodiments, the electrodes 110, 120, 130 may be arranged concentrically and may comprise a reaction site of a microenvironment. For example, the cathode electrode 110 may surround and be concentric with the anode electrode 120, which in turn may surround and be concentric with the sensing electrode 130. With such an arrangement, the cathode electrode 110 may function as an electrochemical “wall” that effectively prevents diffusion of protons (H ⁺ ) generated at the anode electrode 120. In some embodiments, the system 1000 may comprise a plurality of pixels each including a set of concentric electrodes 110, 120, 130. Each pixel may correspond to an individual reaction site for an electrochemical reaction. The cathode electrodes 110 of the pixels may allow localized control of the individual reaction sites corresponding to the pixels. The OCV of a pixel, which may be measured by the pixel’s sensing electrode 130, may be proportional to the concentration of protons, i.e., the pH, of the microenvironment within pixel.

[0048] The CMOS electronics 1005 may comprise active circuitry formed in and/or on the semiconductor substrate 1003, including one or more stimulus source circuits 1005a, 1005b and one or more recording/sensing circuits 1005c. According to some embodiments of the present technology, the one or more of the stimulus source circuits 1005a, 1005b may include one or more current sources (e.g., current injectors), or one or more voltage sources, or a combination thereof. In some embodiments, the cathode electrode 110 may be connected to a negative voltage source or a current sink 1005a, the anode electrode 120 may be connected to a positive voltage source or a current source 1005b, and the sensing electrode 130 may be connected to OCV measurement circuitry 1005c. Although FIG. 1 shows portions of the CMOS electronics 1005 to be located in the semiconductor substrate 1003 underneath the electrodes 110, 120, 130, it should be understood that some portions of the CMOS electronics 1005 may be located elsewhere in/on the semiconductor substrate and need not be located underneath the electrodes 110, 120, 130.

[0049] According to some embodiments of the present technology, the electrodes 110, 120, 130 of the electrochemical cell 1002 may be reconfigured using the CMOS electronics 1005. In some embodiments, the CMOS electronics 1005 may include routing and switching components that may be programmed to connect a selected electrode of the electrochemical cell 1002 to a stimulus source circuit, or to a recording/sensing circuit (e.g., to measure a voltage or a current), or to other circuit components to provide different functionalities. In some embodiments, the CMOS electronics 1005 may provide signals to and receive signals from the processing system 1006. For example, the processing system 1006 may receive a signal corresponding to an OCV detected by the sensing electrode 130 and may provide control signals to control a stimulus current and/or a stimulus voltage provided to the anode and cathode electrodes 120, 110. In some embodiments, the processing system 1006 may be used to pre-program configuration bits in a configuration memory (not shown) of the electrochemical cell 1002, to allow an electrochemical process to run automatically based on the configuration bits. In some embodiments in which the system 1000 may include a plurality of pixels each comprised of its own configuration memory, configuration bits stored in a configuration memory of a pixel may be different from configuration bits stored in a configuration memory of another pixel, such that each pixel may be stimulated differently from another pixel of the system 1000. In some embodiments, a group of pixels may each store the same configuration bits, such that all the pixels of the group may be stimulated in the same way or nearly the same way. In some embodiments, the CMOS electronics 1005 of the system 1000 may include a shared circuitry portion, which may comprise circuitry that is shared among the group of pixels, and also may include individual circuitry portions, which may comprise circuitry that corresponds to the pixels of the group individually. The electrodes 110, 120, 130 for each pixel of the group may be controlled individually by the individual circuitry portions of the CMOS electronics 1005 and/or may be controlled collectively by the shared circuitry portion of the CMOS electronics 1005, directly or via the individual circuitry portions. In some embodiments, the processing system 1006 may be used to perform random-access programming of one or more pixels by addressing the configuration memory of each of the one or more pixels to store an electrochemical configuration for a desired electrochemical-reaction process.

[0050] The electrochemical cell 1002 may be a semiconductor chip comprising integrated circuits and other reaction-site components fabricated in and/or on a semiconductor substrate (e.g., a wafer), according to some embodiments of the present technology, and may be referred to as a “chip” herein. In some embodiments, the electrochemical cell 1002 may be one of many electrochemical cells 1002 produced from a semiconductor wafer using known large-scale integration techniques. In some embodiments, the chip 1002 may be mounted on a carrier (e.g., a PCB) that is operatively connected to the processing system 1006. For example, bond wires and/or connections formed from other types of connection techniques may electrically connect components of the CMOS electronics 1005 of the electrochemical cell 1002 to wiring traces of the carrier.

[0051] According to some embodiments of the present technology, a chip may comprise a plurality pixels and chip circuitry. Each pixel may comprise one or more electrode arrangements and a pixel circuit. The chip circuitry may be shared electronic circuitry that is common to some or all of the pixels, and the pixel circuits may be electronic circuitry that each is dedicated to interacting with its corresponding electrode arrangement.

[0052] FIGs. 2A and 2B schematically depict a chip 3 comprised of an array 4 of pixels 30 and chip circuitry located at a periphery surrounding the array 4, according to some embodiments of the present technology. In some embodiments, the chip 3 may correspond to a well of an electrochemical apparatus. In some embodiments, the chip may correspond to a flow cell of an electrochemical apparatus. The pixels 30 of the array 4 may be arranged in n rows and m columns. In some cases m = n, such that the array 4 may be square-shaped. CMOS circuitry (e.g., various components of the CMOS electronics 1005 discussed above) may be formed in peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d surrounding the array 4. In some embodiments, m column shift registers may be formed in a plurality of first circuitry regions 14a, 14b, and n row shift registers may be formed in a plurality of second circuitry regions 15a, 15b.

[0053] According to some embodiments of the present technology, shift registers for even-numbered columns may be located in a first circuitry region 14a on a first peripheral side of the array 4, shift registers for even-numbered rows may be located in a second circuitry region 15a on a second peripheral side of the array 4, shift registers for odd- numbered columns may be located in a first circuitry region 14b on a third peripheral side of the array 4, and shift registers for odd-numbered rows may be located in a second circuitry region 15b on fourth peripheral side of the array 4, as depicted in FIG. 2B. Such an odd/even arrangement may be advantageous for localizing driving circuitry for the rows and columns to regions dedicated for particular rows (e.g., odd row or even rows) or particular columns (e.g., odd columns or even columns), such that some circuitry may be shared to conserve space on the chip 3. In some embodiments, some or all of the pixels 30 of the array 4 may each be addressed and/or controlled individually by appropriate selection of one of the column shift registers of the first regions 14a, 14b and one of the row shift registers of the second regions 15a, 15b. In some embodiments, a chip architecture of the chip 3 may be such that the array 4 of pixels 30 covers around 85% to 90% of a total area of a surface of the chip 3, with a remainder of the total area comprising circuitry, wiring, and/or other components for addressing the pixels 30 and for transmitting power and/or signals within the chip 3. In some embodiments, the chip architecture of the chip 3 may be such that the array 4 covers at least 90% of the total area (e.g., 90% to 95%). As will be appreciated, a chip having a relatively larger area for a pixel array may permit the pixel array to have larger pixels and/or a greater number of pixels, compared with a chip having a relatively smaller area for a pixel array. In some embodiments, a total number of pixels 30 in the array 4 may be in a range of 10,000 to 1,500,000 (e.g., 10,000 to 100,000; 100,000 to 150,000; 150,000 to 500,000; 500,000 to 1,000,000; 1,000,000 to 1,500,00).

[0054] The chip 3 may include CMOS circuitry that is not located in the peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d. As discussed in more detail below, some or all of the pixels 30 may each include a pixel circuit, which may be located adjacent corresponding electrodes. In some embodiments, some or all of the pixel circuits may each include memory configured to store an electrochemical configuration for a corresponding pixel 30 as well as switches and circuit components for controllably and selectively stimulating electrodes of the corresponding pixel 30. The electrochemical configuration may include a magnitude, a direction, and a stimulation type (e.g., voltage or current) for a desired reaction. In some embodiments, a computer external to the chip 3 and operatively connected to the chip 3 (e.g., via the CMOS circuitry of the chip 3) may be used to perform randomaccess programming of a desired group of one or more of the pixels 30 of the array 4, by addressing the memories of the pixels 30 of the group to store an electrochemical configuration for a desired reaction.

[0055] The chip 3 may be analogous, in some respects, to the electrochemical cell 1002. For example, the electrochemical cell 1002 may correspond to the chip 3 comprised of a single pixel 30.

[0056] In some embodiments of the present technology, the CMOS electronics 1005 may be controlled to stimulate one of the anode and cathode electrodes 120, 110 of the pixel and to simultaneously detect an OCV using the sensing electrode 130 and thus monitor progress of an electrochemical reaction in a microenvironment of the pixel 30. In some embodiments, a group of one or more pixels 30 of an array 4 may be controlled to perform one type of electrochemical reaction while another group of one or more pixels 30 of the array 4 may be controlled to perform another type of electrochemical reaction simultaneously.

[0057] According to some embodiments of the present technology, the semiconductor substrate 1003 may be comprised of Si. In such embodiments, the CMOS electronics 1005 may be comprised of an integrated circuit fabricated using standard CMOS processing techniques. The electrochemical cell 1002 may be disposed within the semiconductor substrate 1003 (e.g., as conductors exposed to the electrochemical solution 1004 at the surface 1003a of the semiconductor substrate 1003). In some embodiments, the surface 1003a may be an insulative surface that provides mechanical support and electrical isolation to the electrochemical cell 1002 while also providing a suitable surface for electrochemical reactions (e.g., chemical synthesis reactions). Although FIG. 1 may show that the electrochemical cell 1002 is partially embedded in the semiconductor substrate 1003, such an arrangement is an illustrative example only and not a requirement. In some embodiments, top surfaces of the electrodes 110, 120, 130 may be above, aligned vertically with, or below the surface 1003a of the semiconductor substrate 1003. Additionally or alternatively, the top surfaces of the electrodes 110, 120, 130 may have a passivation or functionalization layer. In some embodiments, holes may be patterned in the passivation or functionalization layer to expose conductive surfaces of the electrodes 110, 120, 130 to the solution 1004. In some embodiments in which the electrodes 110, 120, 130 correspond to a pixel 30 of an array 4 of pixels 30 (e.g., see FIG. 2A), holes may be patterned in the passivation or functionalization layer for some but not all of the pixels 30 of the array 4, to allow those pixels 30 to be monitored.

[0058] The semiconductor substrate 1003 is not limited to being a Si-based substrate and may be any substrate fabricated using know semiconductor processing techniques. For example, the semiconductor substrate 1003 may be comprised of a group IV semiconductor, a III-V semiconductor, a II-V semiconductor, a sp ² hybridized carbon material, a chalcogenide, a metal, a metallic compound, an oxide, a nitride, a silicide, a polymer material, or combinations thereof. The semiconductor substrate 1003 may be comprised of a unitary component or may be comprised of a composite of multiple components. Components in the semiconductor substrate 1003 may include, e.g., one or more active circuit layers, one or more wiring layers, one or more redistribution layers, a circuit board, or combinations thereof. Components in the semiconductor substrate 1003 may be formed during or in addition to CMOS processing, or be formed separately and bonded together using, e.g., packaging techniques known in the field of semiconductor processing.

Conductors may be provided in the semiconductor substrate 1003 and patterned to interconnect circuitry of the CMOS electronics 1005 with the electrodes 110, 120, 130 of the electrochemical cell 1002.

[0059] According to some embodiments of the disclosed technology, connection points (e.g., contact pads) may be provided on the semiconductor substrate 1003 (e.g., at a bottom surface of the semiconductor substrate 1003, at a peripheral edge of the semiconductor substrate 1003) for electrically interfacing components within the semiconductor substrate 1003 directly or indirectly with the processing system 1006. Electrical connection between the processing system 1006 and the semiconductor substrate 1003 may be provided via any suitable means (e.g., known chip-connection techniques, wire bonding, printed-circuit-board (“PCB”) connectors, flexible cables, wireless communication, etc.). In some embodiments, the semiconductor substrate 1003 may be wire-bonded to a PCB carrier, which in turn may be operatively connected to the processing system 1006.

[0060] In some embodiments of the present technology, operation of the electrochemical cell 1002 may be automated (e.g., under control of the processing system 1006). Referring back to FIG. 1, the processing system 1006 of the electrochemical system 1000 may, in some embodiments, include a computer 1006a comprised of a storage medium/media 1006b, memory 1006c, and at least one processor 1006d. The storage medium/media 1006b and the memory 1006c may include any suitable non-transitory computer-readable medium, nonlimiting examples of which include a computer hard-disk and/or solid-state memory, compact disc(s), optical disc(s), magnetic tape(s), flash memory device(s), circuit configurations in Field Programmable Gate Arrays (FPGAs) or other semiconductor devices, as well as other tangible structures for storing computer-readable code. In some embodiments, the storage medium/media 1006b may include a non-volatile storage, and the memory 1006c may be comprised of a volatile storage. In some embodiments, computer-executable instructions may be loaded from the storage medium/media 1006b to the memory 1006c before execution by the processor 1006d to perform some or all steps or acts of various methods of, e.g., steps or acts to control an electrochemical synthesis reaction. However, as will be appreciated, a distinction between the storage medium/media 1006b and the memory 1006c is not critical and either or both may be present in some embodiments.

[0061] The processor 1006c may be any suitable processing device, non-limiting examples of which include: a central processing unit (CPU), a digital signal processor (DSP), a controller, an addressable controller, a general microprocessor, a special purpose microprocessor, a microcontroller, an addressable microprocessor, a programmable processor, a programmable controller, a dedicated processor, a dedicated controller, any other suitable processing device. As will be appreciated, the processor 1006d may be comprised of a combination of these devices and/or multiple units of one of these devices. Some or all components within the processing system 1006 may be packaged as a system-on-a-chip (SOC). Moreover, it should be appreciated that FIG. 1 shows a schematic representation of the processing system 1006. In some embodiments of the present technology, the processing system 1006 may be comprised of units for performing distributed processing. In some embodiments, the processing system 1006 may be configured to control an overall flow of a synthesis method performed by the system 1000, including mapping of OCV measurements over time from electrodes, analysis of results, etc. [0062] According to some embodiments of the present technology, the electrochemical cell 1002 may be patterned on the surface 1003 a as part of a semiconductor fabrication process to form the chip 3. The electrodes 110, 120, 130 of the electrochemical cell 1002 may include conductive structures (e.g., pads, shaped structures, annular structures, etc.) that may be formed of a metal (e.g., Au, Pt, Au-Pt alloys, etc.). In some embodiments, the electrodes 110, 120, 130 of the electrochemical cell 1002 may be comprised of an inert material that is non-reactive with the electrochemical solution 1004. For example, the conductive structures may be formed of Al with plated Au as a top layer exposed to the solution 1004. In such embodiments, the semiconductor substrate 1003 may be comprised of conductors that interconnect the exposed electrodes 110, 120, 130 of the electrochemical cell 1002 to circuitry and other electrical components within the substrate 1003.

[0063] In some embodiments of the present technology, the electrodes 110, 120, 130 may be fabricated during or after a CMOS -compatible fabrication process to form the CMOS electronics 1005, such that the electrodes 110, 120, 130 may be located above portions of the CMOS electronics 1005.

[0064] Returning to FIG. 2A, the chip 3 may be used for spatially positioned electrochemical reactions by selectively addressing certain portions of the pixel array 4, according to some embodiments of the disclosed technology. For example, the electrodes 110, 120, 130 of a group of pixels 30 in the pixel array 4 may be selected for monitoring and/or to receive one or more applied currents, via the CMOS circuitry of the chip 3. The current(s) may be chosen to initiate an electrochemical reaction in regions of a solution directly above the selected electrodes 110, 120, 130 and/or to investigate whether an electrochemical reaction may be initiated. As will be appreciated, electrochemistry can be performed selectively at a pre-designed spatial pattern, based on the size, shape, and distribution of the selected pixels 30 of the chip 3 by selectively addressing the electrodes 110, 120, 130 of the selected pixels 30 using the CMOS circuitry.

[0065] FIG. 3 schematically depicts a block diagram of an electrochemical system 1, according to various embodiments of the present technology. The electrochemical system 1 may comprise a chip apparatus 2 operatively connected to a host system 50. The chip apparatus 2 may include a single chip 3 or a plurality of chips 3. One or more of the chips 3 may each comprise chip circuitry 5 and an array 4 of pixels 30 operatively connected to the chip circuitry 5. The chip circuitry 5 may comprise driver circuits for driving stimulation of the pixels 30 and/or for driving read-out of signals from the pixels 30. In some embodiments in which the chip apparatus 2 includes multiple chips 3, at least some of the chips 3 may be disposed on a common substrate. For example, the chips 3 may be formed from and supported by a common semiconductor substrate (e.g., a portion of a single wafer) and may be contiguous with each other. The chip 3 may, e.g., be a IM chip that includes at least one million pixels 30.

[0066] FIG. 4A schematically depicts a perspective view of a structure of a pixel 30, according to some embodiments of the present technology. The pixel 30 may include an electrode arrangement 100 overlaying and operatively connected to a pixel circuit 200 corresponding to the electrode arrangement 100. FIG. 4B schematically depicts a plan view of the electrode arrangement 100. In some embodiments, the electrode arrangements 100 of the pixels 30 of the array 4 may be arranged in a first array, and the pixel circuits 200 may be arranged in a second array located under the first array in a stacked structure, with some or all of the electrode arrangements 100 of the first array being operatively connected to some or all of the pixel circuits 200 of the second array respectively, in a corresponding manner. As depicted in FIG. 4B, each electrode arrangement 100 may include a plurality of electrodes 110, 120, 130. The electrode arrangement 100 may be located on an electrode level 101 of the chip 3. In some embodiments, the electrode level 101 of the chip 3 may be an outer surface of the chip 3, thus enabling the electrodes 110, 120, 130 to be exposed to a solution or medium (e.g., the electrochemical solution 1004 discussed above). The pixel circuits 200 may be arranged on a pixel-circuitry level 202 of the chip 3 below the electrode level 101.

[0067] According to some embodiments of the present technology, the electrodes 110, 120, 130 of at least some of the electrode arrangements 100 may be comprised of first and second stimulation electrodes 110, 120 and a sensing electrode 130. In some embodiments, the first stimulation electrode 110 may be a cathode electrode 110 and the second stimulation electrode 120 may be an anode electrode. In some other embodiments, the first stimulation electrode 110 may be an anode electrode 110 and the second stimulation electrode 120 may be a cathode electrode.

[0068] According to some embodiments of the present technology, the first and second stimulation electrodes 110, 120 of at least some of the pixels 30 may be structured as concentric rings that may have a common region 150. The sensing electrode 130 may be located within the common region 150, as schematically shown in FIG. 4B. In some embodiments, the first and second stimulation electrodes 110, 120 may be connected to portions of the chip circuitry 5 configured to control application of potentials to the stimulation electrodes 110, 120 (e.g., via the pixel circuit 200 of the pixel 30), and the sensing electrode 130 may be connected to portions of the chip circuitry 5 configured to read out a signal sensed by the sensing electrode 130.

[0069] In some embodiments of the present technology, the first and second stimulation electrodes 110, 120 may be a cathode electrode 110 and an anode electrode 120, which may be used to manipulate localization of electrochemical reagents. For example, the cathode electrode 110 and anode electrode 120 may be used to obtain a desired reaction rate by controlling an anodic or cathodic current flowing at one or another of the electrodes 110, 120. In some embodiments, an OCV of a pixel 30 may be measured between the sensing electrode 130 of the pixel 30 and the cathode electrode 110 or the anode electrode 120. By measuring the OCV of a pixel 30 during an electrochemical reaction, a progress of the electrochemical reaction may be monitored in real time while stimulation of the pixel 30 is occurring. In some embodiments, the OCVs for each pixel 30 of a group of pixels 30 or even of the entire array 4 may be monitored in real time during an electrochemical reaction (e.g., before, during, and after stimulation of the pixels 30).

[0070] As noted above, the array 4 may include pixel groups. In some embodiments of the technology disclosed herein, different pixel groups may be stimulated differently. For example, a first pixel group may be stimulated with a first anode stimulation current or a first cathode stimulation current while a second pixel group may be stimulated with a second anode stimulation current or a second cathode stimulation current.

[0071] According to some embodiments of the disclosed technology, for some or all of the chips 3 of the electrochemical system 1, the chip circuitry 5 may comprise a plurality of shift registers 24a, 24b, 26a, 26b, operatively coupled to the pixels 30 of the array 4, to allow each pixel 30 of at least some of the pixels 30 of the array 4 to be individually controlled, and a clock generator 9 configured to provide non-overlapping clock signals to the pixels 30 of the array 4. Buffers 17 may be provided for buffering the clock signals from the clock generator 8. In some embodiments, the shift registers 24a, 24b, 26a, 26b and the clock generator 9 may operate to control stimulation of the stimulation electrodes 110, 120 of some or all of the pixels 30 of the array 4. The chip circuitry 5 for some or all of the chips 3 may include amplifiers 7 and a multiplexer 8 for amplifying and reading out signals sensed by the sensing electrodes 130 of some or all of the pixels 30 of the array 4. A configuration memory 10 of the chip circuitry 5 may store configuration bits for controlling a read-out process of the multiplexer 8 and the amplifiers 7. In some embodiments, the multiplexer 8 may comprise a channel multiplexer and the amplifiers 7 may comprise read-out channels for reading out and amplifying signals from respective channels or groups of pixels 30 of the array 4. In some embodiments, each amplifier 7 may comprise a multiplexer (not shown) configured to allow signals from individual pixels 30 to be read from a channel or group of pixels corresponding to the amplifier 7. The multiplexer 8 may be operatively connected to the amplifiers 7 and the host system 50 to allow the host system 50 to read out one or more signals selectively from one or more pixels 30 of the array 4 and/or to read out signals from one or more channels or groups of pixels 30 of the array 4.

[0072] According to some embodiments of the disclosed technology, the host system 50 may be operatively connected to the chip circuitry 5 of each of the chips 3 of the chip apparatus 2, as depicted in FIG. 3. The host system 50 may be configured to provide stimulation control signals to the clock generator 9 and the shift registers 24a, 24b, 26a, 26b to stimulate the pixels 30 of the array 4. The host system 50 also may be configured to provide sensor control signals to the multiplexer 8 and the amplifiers 7. In some embodiments, the host system 50 may update the configuration bits stored in the configuration memory 10, which may control the read-out process of the multiplexer 8 and the amplifiers 7. The host system 50 may include a controller computer 51 comprised of at least one microprocessor (e.g., CPU(s)) operatively coupled to at least one storage device (e.g., hard disk(s), solid-state memory device(s), etc.) storing computer-readable code. The microprocessor(s) may be configured to execute the computer-readable code to control one or more operations or procedures of the chip apparatus 2. For example, the microprocessor(s) may execute the computer-readable code to control an electrochemical stimulation procedure to stimulate the pixels 30, and/or to control a recording procedure to record measurement data obtained from the pixels 30, and/or to control a display device (not shown) to display a user interface to allow a user to input parameters for controlling the chip apparatus 2 (e.g., to control the electrochemical stimulation procedure, to control the recording procedure, etc.). In some embodiments, the user interface may allow a user to input configuration parameters for configuring the chip apparatus 2 and/or the host system 50.

[0073] In some embodiments of the present technology, the host system 50 may include a FPGA 52 operative coupled between the controller computer 51 and the chip circuitry 5 of the chips 3 of the multi-chip apparatus 2. In some embodiments, the FPGA 52 may be configured to receive input parameters from the controller computer 51 (e.g., the parameters inputted by the user) and to output control signals to the chip circuitry 5 based on the input parameters. For example, the FPGA 52 may be operatively connected to the clock generators 9 of the chips 3 to provide signals for controlling the clock generators 9 to generate nonoverlapping clock signals. The FPGA 52 may be operatively connected to the multiplexers 8 of the chips 3, to receive measurement data obtained from the pixels 30 of the chips 3. An analog-to-digital converter 53 may be provided between the multiplexers 8 and the FPGA 52 to digitize the measurement data obtained from the pixels 30. In some embodiments, the FPGA 52 may be configured to aggregate the measurement data before the measurement data is recorded by the controller computer 51. In some embodiments, the FPGA 52 may be operatively connected to the configuration memories 10 of the chips 3 to program the configuration memories 10.

[0074] According to some embodiments of the present technology, the electrochemical system 1 may include at least one temperature sensor 11 configured to measure a temperature of a reaction surface of the array 4. In some embodiments, some or all of the chips 3 of the chip apparatus 2 may each comprise a temperature sensor 11 as part of the chip circuitry 5. In some embodiments, the temperature sensor 11 may output a temperature signal to the ADC 53, which in turn may provide a digital temperature signal to the FPGA 52. In some embodiments, the temperature sensor 11 may include a temperature-to-frequency converter circuit configured to output a digital temperature signal directly to the FPGA 52.

[0075] FIG. 5 schematically depicts a scalable architecture for the chip 3, according to some embodiments of the present technology. As noted above, the peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d surrounding the array 4 of pixels 30 may include circuitry shared by the pixels 30 (see FIGs. 2A and 2B). The architecture may comprise a plurality of chip sections, with the pixels 30 of the array 4 being divided into subsets respectively corresponding to the chip sections. In some embodiments, the chip sections may comprise four quadrants 20, one at each comer of the array 4, with each quadrant including a quarter of the array 4. As depicted in FIG. 5, each quadrant 20 may include portions of two of the peripheral regions on adjacent sides of the array 4. A first (top left) quadrant may include a first quad corner region 16a and portions of the peripheral regions 14a, 15a; a second (top right) quadrant may include a second quad comer region 16b and portions of the peripheral regions 14a, 15b; a third quadrant (bottom left) may include a third quad comer region 16c and portions of the peripheral regions 15a, 14b; and a fourth (bottom right) quadrant may include a fourth quad corner 16d and portions of the peripheral regions 14b, 15b. In some embodiments, the peripheral region 14a may comprise a plurality of column drivers 23a and a plurality of shift registers 24a for the first and second quadrants; the peripheral region 14b may comprise a plurality of column drivers 23b and a plurality of shift registers 24b for the third and fourth quadrants; the peripheral region 15a may comprise a plurality of row drivers 25a and a plurality of shift registers 26a for the first and third quadrants; and the peripheral region 15b may comprise a plurality of row drivers 25b and a plurality of shift registers 26b for the second and fourth quadrants.

[0076] According to some embodiments of the disclosed technology, each of the column drivers 23 a, 23b and each of the row drivers 25a, 25b may comprise least one buffer 17 configured to store at least one non-overlapping clock signal generated by the clock generator 9. In some embodiments, each of the quad corner regions 16a, 16b, 16c, 16d may comprise some of or all of: a multiplexer 8, at least one amplifier 7, a temperature sensor 11, a configuration memory 10, and a current generator for generating a reference current. In some embodiments, the quad comer regions 16a, 16b, 16c, 16d may comprise analog circuits of the chip circuitry 5. In some embodiments, the pixels 30 of a quadrant 20 may be driven by circuitry of the quadrant 20. For example, as depicted in the enlarged portion of FIG. 5 showing the first quadrant, the pixels 30 in the portion 4a of the array 4 located in the first quadrant may be controlled by circuitry in the first quad comer region 16a, the column drivers 23 a and the shift registers 24a in the portion of the peripheral region 14a corresponding to the first quadrant, and the row drivers 25a and the shift registers 26a of the portion of the peripheral region 15a corresponding to the first quadrant. For each quadrant 20, the column drivers, the row drivers, and the shift registers of the quadrant 20 may be used to address the pixels 30 of the quadrant individually or collectively. In some embodiments, for each quadrant 20, each column of the pixels 30 of the quadrant 20 may be aligned with the column driver 23a, 23b and the shift register 24a, 24b corresponding to the column, and each row of the pixels 30 of the quadrant 20 may be aligned with the row driver 25a, 25b and the shift register 26a, 26b corresponding to the row. The second, third, and fourth quadrants may have similar arrangements, in some embodiments. Such alignment and arrangement of the chip circuitry 5 for the quadrants 20 may advantageously minimize an amount of area used for interconnecting the pixels 30 with portions of the chip circuitry 5 in the peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d. In some embodiments, the buffers 17 may comprise column buffers and/or row buffers, with each buffer 17 being configured to buffer a non-overlapping clock signal for pixels of a corresponding column or a corresponding row of the array 4. Each buffer 17 may be operatively connected to pixels 30 of the corresponding column or row of the array 4 such that the non-overlapping clock signals in the buffer 17 may be used to control a pixel stimulation process in the corresponding pixels 30.

[0077] According to some embodiments of the present technology, the chip 3 may include a pad ring 41 comprised of a plurality of contact pads (not shown) connected to the chip circuitry 5. As depicted in FIGs. 2A and 2B, the pad ring 41 may be located at or near an outer edge of the chip 3. The contact pads of the pad ring 41 may allow the chip circuitry 5 to communicate with external electronic circuitry (e.g., for power and/or signal transmissions). In some embodiments, the contact pads of the pad ring 41 may be used to transmit power and/or signals to, and/or to receive power and/or signals from, an external device via, e.g., bond wires attaching the external device to the contact pads. For example, the chip 3 may be mounted on a PCB carrier comprised of wiring configured to carry signals and/or power to/from the chip 3. The contact pads of the pad ring 41 may be electrically connected to the wiring (e.g., by wire bonding and/or another connection technique) to the wiring of the PCB carrier.

[0078] In some embodiments of the present technology, the chip 3 may include a routinggutter ring 42 located between the pad ring 41 and the peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d surrounding the array 4 of pixels 30. The routing-gutter ring 42 may be configured to transmit power and/or signals between the contact pads of the pad ring 41 and the chip circuitry 5 of the chip 3. In some embodiments, the routing-gutter ring 42 may include a plurality of routing-gutter conduits 42a configured to transmit power and/or signals between circuitry in the peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d, the pixel circuits 200 of the pixels 30 of the array 4, and the contact pads of the pad ring 41. In some embodiments, the chip 3 may include one or more routing-gutter rings (not shown) in addition to the routing-gutter ring 42.

[0079] As noted above, the architecture of the chip 3 may be scalable. According to some embodiments of the disclosed technology, the chip apparatus 2 of the electrochemical system 1 may be configured as an array of chips 3 arranged in columns and rows. In some embodiments, the array of chips 3 may include chips 3-11, 3-12, 3-13, 3-14 arranged as adjacent tiles, as schematically depicted in FIG. 6. The chips 3-11, 3-12, 3-13, 3-14 may be formed from and supported by a common semiconductor substrate. For example, the chip apparatus 2 may comprise a single semiconductor wafer from which the chips 3 are formed via wafer-scale integration techniques. In some embodiments, the chips 3-11, 3-12, 3-13, 3- 14 may be interconnected by wiring (not shown) configured to transmit control signals from the host system 50 to each of the chips 3-11, 3-12, 3-13, 3-14, such that electrochemical processes may be initiated and controlled simultaneously for the pixels 30 of the chips 3-11, 3-12, 3-13, 3-14. In some embodiments, the chips 3-11, 3-12, 3-13, 3-14 may be interconnected by signal repeaters 6a, 6b configured to transfer control signals, either via direct wiring (e.g., chip-to-chip wiring or board-to-chip wiring) or alternatively via wireless board-to-board connections, to adjacent chips 3, 3-11, 3-12, 3-13, 3-14. The signal repeaters 6a, 6b may be comprised of buffers, in some embodiments. For example, row-control signals may be transferred from the third quadrant of the chip 3-11 to the first quadrant of the chip 3- 13 via row signal repeaters 6a located in the first and third quadrants of the chips 3-11, 3-13, and row-control signals may be transferred from the fourth quadrant of the chip 3-11 to the second quadrant of the chip 3-13 via row signal repeaters 6a located in the second and fourth quadrants of the chips 3-11, 3-13. Similar arrangements may be made for transferring column-control signals via column signal repeaters 6b in the quadrants of the chips 3-11, 3- 12, 3-13, 3-14. In FIG. 6, the row signal repeaters 6a are represented by downward-pointing arrows, and the column signal repeaters 6b are represented by rightward-pointing arrows. In some embodiments, circuitry for the row and column signal repeaters 6a, 6b may be included in each of the quad comer regions 16a, 16b, 16c, 16d.

[0080] As will be appreciated, the chips 3-11, 3-12, 3-13, 3-14 of the chip apparatus 2 need not be formed from and supported by a common semiconductor substrate. In some embodiments of the present technology, one or more of the chips 3-11, 3-12, 3-13, 3-14 may be formed individually on one or more semiconductor substrates different from a remainder of the chips 3-11, 3-12, 3-13, 3-14.

[0081] FIG. 7 shows a diagram of the pixel circuit 200, according to some embodiments of the present technology. The pixels circuit 200 may be operatively connected to the clock generator 9. In some embodiments, the clock generator 9 may be configured to output first and second clock signals <J>i, $2, which may be non-overlapping signals. The pixel circuit 200 may be include a voltage stimulator 202 and a current stimulator 204 configured to provide, selectively, voltage stimulation or current stimulation. The voltage stimulator 202 may be configured to receive a voltage signal VN (or Vp) from a voltage generator (not shown) and to output a stimulation voltage. The current stimulator 204 may be configured to receive the voltage signal VN (or Vp) from the voltage generator and to output a stimulation current. The current stimulator 204 may include a switched capacitor 206 controlled by clock signals <J>i, $2 from the clock generator 9. The clock signals <J>i, $2 may comprise a first clock signal configured to control a first switch 208a and a second clock signal $2 configured to control a second switch 208b. The clock signals clock signals $1, $2 may be non-overlapped clock signals, as depicted in the inset diagram in FIG. 7, and may allow the stimulation current provided by the current stimulator 204 to have a resolution as fine as 0.1 nA at a clock resolution of 10 kHz. The resolution of current stimulation may be further extended by increasing the clock resolution, whose source is provided by the FPGA 52 or, in some embodiments, an off-chip clock generator. In some cases, the current-stimulation resolution may be increased such that it is limited by the CMOS leakage current. Details regarding use of clock signals to control current resolution may be found in International Application No. PCT/US2022/033228, which is incorporated by reference herein in its entirety.

[0082] According to some embodiments of the present technology, the pixel circuit 200 may be configured as shown in FIG. 8. In some embodiments, the clock generator 9 may be configured to output first and second anode clock signals $i _a , $2a, which may be nonoverlapping signals, and first and second cathode clock signals $i _c , $2c, which may be nonoverlapping clock signals. The clock generator 9 also may include circuitry to output complementary clock signals, which may be complements of the first and second anode clock signals $ia, $2a and complements of the first and second cathode clock signals $ ic, $2c. In some embodiments, each pixel circuit 200 of the pixels 30 of the array 4 may include a cathode stimulator 252, an anode stimulator 254, a switch system 210 comprising a plurality of switches Si, S2, S3, S4, 211, 212, and an in-pixel memory 207 storing configuration bits for enabling access or connection to the electrodes 110, 120, 130 of the pixel 30 corresponding to the pixel circuit 200. The cathode stimulator 252 may be configured to receive a cathode voltage signal VN from a voltage generator (not shown), a first enable signal En from a pixel memory 207 corresponding to the pixel circuit 200, and a first cathode clock signal (j)i _c from the clock generator 9, and to output a cathode stimulation current to a first stimulation electrode 110, which may serve as the cathode of the electrode arrangement 100 corresponding to the pixel circuit 200, via a switched capacitor 206c and the switch system 210. The switched capacitor 206c may be activated by clock signals $i _c , $2c from the clock generator 9. The anode stimulator 254 may be configured to receive an anode voltage signal Vp from a voltage generator (not shown), a second enable signal En from the pixel memory 207, and a complementary first anode clock signal (j)i _a from the clock generator 9, and to output an anode stimulation current to a second stimulation electrode 120, which may serve as the anode of the electrode arrangement 100 corresponding to the pixel circuit 200, via a switched capacitor 206a and the switch system 210. The first and second enable signals En, En may be complements of each other. The switched capacitor 206a may be activated by clock signals $i _a , $2a from the clock generator 9. As will be appreciated, signals from the clock generator 9 may be via the buffers 17, which may improve the switching speed of clock signals distributed to the pixel circuits 200 in the array 4.

[0083] The switches Si, S2, S3, S4, 211, 212 of the switch system 210 may be configured to operate based on the first and second enable signals En, En and configuration bits stored in the in-pixel memory 207. The in-pixel memory 207 may be operatively connected to the cathode stimulator 252, the anode stimulator 254, and the switch system 210 to selectively cause selection of a cathode stimulation signal (current or voltage) to be provided to by the cathode stimulator 252 to one of the stimulation electrodes 110, 120 or selection of an anode stimulation signal (current or voltage) to be provide by the node stimulator 254 to one of the stimulation electrodes 110, 120. For example, the first and second enable signals En, En may cause a first output switch 211 to be closed and a second output switch 212 to be open, to allow the first stimulation electrode 110 to be provided the stimulation signal from the cathode stimulator 252, or may cause the first output switch 211 to be open and the second output switch 212 to be closed, to allow the second stimulation electrode 120 to be provided the stimulation signal from the anode stimulator 254, thus enabling pixel stimulation.

[0084] According to some embodiments of the present technology, a pixel 30 may be “initialized” by sweeping the electrodes 110, 120, 130 of the pixel 30 with a cleaning voltage Vdean. In some embodiments, the cleaning voltage may be applied at a node 213 of the switch system 210, and switches Si, S2, S3, S4, 211, 212 of the switch system 210 may be operated to isolate the electrodes 110, 120, 130 of the pixel 30 from the pixel circuit 200 during an initialization sweep. In some embodiments, the cleaning voltage Vdean may be provided to the pixel circuit 200 by a voltage generator (not shown) via wiring that may bypass or be disconnected from the cathode and anode stimulators 252, 254. For example, during an initialization sweep, the switches S3, S4, 211, 212 may be controlled to be open while the switches Si, S2 may be controlled to be closed, thus enabling the cleaning voltage Vdean to be applied to the electrodes 110, 120, 130 in isolation from the cathode and anode stimulators 252, 254. In some embodiments, the switches Si, S2 of all the pixels 30 or a group of the pixels 30 of the array 4 may be controlled simultaneous by a cleaning signal Clean_en from the host system 50, such that the electrodes 110, 120, 130 of all the pixels 30 or the group of pixels 30 may be swept with the cleaning voltage Vdean simultaneously prior to beginning an electrochemical process. In some embodiments, the cleaning voltage Vdean may be used to globally trigger or activate a uniform initialization of all electrode surfaces with a same voltage at an entire array level via cyclic voltammetry. In some embodiments, a value of the cleaning voltage Vdean may be selectively adjustable by the host system 50 such that a first group of the pixels 30 may be swept with a first voltage while a second group of the pixels 30 may be swept with a second voltage different from the first voltage. As will be appreciated, by appropriately addressing the pixels 30 of the array 4 via the shift registers 24a, 24b, 26a, 26b, any combination of the pixels 30 of the array 4 may undergo an initialization sweep. In some embodiments, the sweeping of the cleaning voltage Vciean may be performed by cyclic voltammetry.

[0085] According to some embodiments of the present technology, the switches S3 and S4 may be used to compensate for leakage currents that may flowing into or out of the electrodes 110, 120 when the pixel 30 is not in use. In some embodiments, to minimize a leakage current when the pixel 30 is not in use (i.e., when the pixel is OFF), the cleaning voltage Vciean may be set to a reference voltage for a solution of an electrochemical process involving other pixels 30 of the chip 3, the switches S3, S4 may be in an open state, and the switches Si, S2 may be in a closed state. This configuration may prevent leakage currents from causing any unwanted electrochemical reactions at unused (OFF) pixels, as the disabled pixels would otherwise have a potential that may drift due to leakage. In some embodiments, this configuration may prevent unwanted initial electrochemical states from being present when the unused pixels are later used in a next programming phase of an electrochemical process. [0086] According to some embodiments of the present technology, a transistor Mi in the cathode stimulator 252 and a transistor M2 the anode stimulator 254 may operate to reduce a quiescent current consumption by 50% in the stimulators 252, 254, by enabling a path of a bias current controlled by bias voltages VN, Vp only when the bias current is used for charging the switched capacitors 206c, 206a. Operation of the transistors Mi, M2 to minimize current consumption and operation of the switches Si, S2, S3, S4, to compensate of leakage currents may be employed advantageously to ensure proper chip operation with minimal power at megapixel scale.

[0087] As noted above, the chip apparatus 2 may comprise a single chip 3 or a plurality of chips 3. According to some embodiments of the present technology, the electrochemical system 1 may be a flow-cell system in which the chip apparatus 2 includes a single chip 3. In some embodiments, the single chip 3 may comprise a plurality of pixels 30 arranged in an array 4 of columns and rows, with a total number of pixels 30 in the array 4 being approximately 120K (120,000) or greater. In some embodiments, the array 4 may include approximately IM (1,000,000) pixels 30 or greater. In some embodiments, the total number of pixels 30 in the array 4 may be in a range of 100K to 500K, or 250K to 750K or 500K to IM, or 750K to 1.25M.

[0088] FIG. 9 schematically depicts a cross section of an electrochemical flow-cell apparatus 500, according to some embodiments of the present technology. The flow-cell apparatus 500 may comprise a single chip 502 mounted on a carrier 504 (e.g., a PCB) and electrically connected to wiring on the carrier 504 by bond wires 506. The chip 502 may be, e.g., a 120K chip. The carrier 504 may be operatively connected to a host system (not shown) configured to control various aspects of electrochemical processes performed by the flow-cell apparatus 500. In some embodiments, the host system of the flow-cell apparatus

500 may be the host system 50. In some embodiments, the chip 502 may be the chip 3 discussed above in connection with FIGs. 2A, 2B, 3, and 5. The flow-cell apparatus 500 may comprise a flow cell 508 configured to provide a reaction chamber in which one or more reaction fluids may flow. A surface of the chip 502 may be exposed to the reaction chamber of the flow cell 508, which may form a fluid-tight interface surrounding pixels of the chip 502. As discussed above in connection with FIG. 1, electrodes of the pixels of the chip 502 may be exposed to a solution (e.g., the solution 1004) in the flow cell 508. In some embodiments, the flow-cell apparatus 500 may include a manifold 510 configured to permit one or more fluids to flow into the reaction chamber of the flow cell 508 and/or may permit fluid in the reaction chamber to flow out of the reaction chamber. In some embodiments, the manifold 510 may be attached to the flow cell 508 by a fluid-tight seal 512 (e.g., an elastomer o-ring or the like).

[0089] FIG. 10A depicts a cross section of an electrochemical flow-cell apparatus 501, according to some embodiments of the present technology. In some embodiments, a top perspective view of the flow-cell apparatus 501 may have a cross section as shown in FIG. 10B. The flow-cell apparatus 501 may comprise a single chip 503 mounted on a carrier 505 (e.g., a PCB) and electrically connected to wiring on the carrier 505 by bond wires 507, which may be operatively connected to a host system (not shown). The chip 503 may be, e.g., a IM chip. The flow-cell apparatus 501 may comprise a reaction chamber 509 in which one or more reaction fluids may flow over pixel electrodes on a surface of the chip 503. The reaction chamber 509 may be bounded at the bottom by the chip 503, at the sides by a bottom portion 51 la of a manifold 511, and at the top by a top portion 51 lb of the manifold 511. The top and bottom portions 51 la, 51 lb of the manifold 511 may form a fluid-tight seal with each other by a gasket 513 (e.g., an elastomer o-ring) which may form a fluid-tight interface surrounding pixels of the chip 502. The top portion 51 lb of the manifold 511 may include an inlet 511c configured to allow fluids to flow into and/or out of the reaction chamber 509. [0090] According to some embodiments of the present technology, the flow-cell apparatus

501 may comprise a housing 515 comprised of a socket bottom 515a and movable a socket top 515b, as shown in FIG. 10B. The housing may be configured to permit an assembly comprised of the carrier 505 and the chip 503 mounted on the carrier 505 to be removed and replaced with another assembly. The socket top 515b may be attached to the socket bottom 515a by a hinge 515c, about which the socket top 515b may pivot relative to the socket bottom 515a, and a latch 515d, which may engage with a portion of the socket top 515b to hold the socket top 515b against the socket bottom 515a such that the top portion 51 lb of the manifold 511 presses the gasket 513 against the bottom portion 51 la of the manifold 511. When the socket top 515b is latched to the socket bottom 515a, the reaction chamber 509 may be ready to receive fluid therein. In some embodiments, a plurality of spring-loaded pins 515d may be provided to ensure that the carrier 505 and/or the chip 503 mounted on the carrier 505 do not experience excessive force during latching of the socket top 515b to the socket bottom 515a, to prevent, e.g., unintentionally disconnecting any of the bond wires 507. In some embodiments, the socket bottom 515a may include a recess 517 configured to receive a temperature-regulated device 520, which may comprise a heater and/or a cooler. In some embodiments, the recess 517 may be a through-hole that permits a lower surface of the carrier 505, opposite to a surface on which the chip 503 is mounted, to be in direct contact with the temperature-regulated device 520 to heat or cool the chip 503 more efficiently during an electrochemical process. In some embodiments, the chip 503 may comprise a temperature sensor (e.g., the temperature sensor 11) configured to indicate whether the pixels of the pixels of the chip 503 are at an appropriate temperature for the electrochemical process.

[0091] It should be understood that although the flow-cell apparatuses 500, 501 are described to include a single chip 502, 503, in some embodiments of the disclosed technology a flow-cell apparatus may include multiple chips (e.g., a plurality of the chips 3).

[0092] According to some embodiments of the present technology, the electrochemical system 1 may be an electrochemical multi- well system in which the chip apparatus 2 includes a plurality of chips 3, such as described herein in connection with FIG. 6, with each of the chips 3 corresponding to a well of the multi-well system. It should be understood that although there are four chips 3-11, 3-12, 3-13, 3-14 shown on FIG. 6, in some embodiments there may be fewer than four chips or greater than four chips. For example, a total number of chips 3 in the chip apparatus 2 may be in a range of from 2 to 30 (e.g., 4, 9, 16, 25). For each chip 3, the array 4 of the chip 3 may include a total number of pixels 30 in a range of 10,000 to 1,500,000 (e.g., 10,000 to 100,000; 100,000 to 150,000; 150,000 to 500,000; 500,000 to 1,000,000; 1,000,000 to 1,500,00). As noted above, the chips 3 of the chip apparatus 2 may be in a tile arrangement such that each chip 3 is in communication with at least one adjacent chip 3 by wiring and/or by signal repeaters 6a, 6b configured to transfer control signals to adjacent chips 3. For example, row-control signals may be transferred from the chip 3 to chip 3 in a row via row signal repeaters 6a located in the quadrants of the chips 3, and columncontrol signals may be transferred from the chip 3 to the chip 3 via column signal repeaters 6b located in quadrants of the chips 3.

[0093] The scalability of the architecture of the chip 3 described herein may allow the electrochemical system 1 to be a wafer-scale multi- well system 1 configured for massively parallel operations. For example, for a multi-well system 1 comprising a wafer bearing a 10 x 10 array of wells or chips 3, (i.e., 100 wells or chips 3), with one million pixels 30 in each well or chip 3, the multi-well system 1 may include 100 million pixels 30. The signal repeaters 6a, 6b may be used advantageously to transfer control signals and configuration signals from row to row of the array of wells and from column to column of the array of wells without requiring individual or specialized signaling to be provided by the host system 50. That is, to the host system 50, the multi-well system 1 comprising 100 million pixels 30 may simply operate as a large device.

[0094] Although operation of 100 million pixels 30 may be straightforward for the host system 50, reading out of OCVs from such a large number of pixels may not be straightforward. For some electrochemical processes, however, it may not be necessary to monitor each pixel 30 of the chip apparatus 2. Instead, a pre-selected subset of the pixels 30 of the apparatus 2 may be designated for monitoring.

[0095] FIG. 11 schematically depicts an arrangement for performing sparse pixel-sensing of a chip 3, according to some embodiments of the present technology. Sparse pixel-sensing may be particularly advantageous for managing sensing from a large number of pixels. In some embodiments, a group of selected pixels 30a of the chip 3 may be selectively monitored through use of a pixel monitoring layer 160. FIG. 12 schematically depicts a cross section of the chip 3, showing the pixel monitoring layer 160 overlaying the electrode arrangements 100 of the array 4 of the chip 3. Openings 32 in the pixel monitoring layer 160 may allow an electrical connection to be made to one or more of the electrodes 110, 120, 130 of each of the selected pixels 30a. In some embodiments, wirings 161 may be formed in a wiring layer and may interconnect the selected pixels 30a with circuitry in one or more of the peripheral regions 14a, 14b, 15a, 15b, 16a, 16b, 16c, 16d surrounding the array 4. For example, the selected pixels 30a may be distributed in the array 4 such that each row and each column includes two of the selected pixels 30a, as depicted in FIG. 11. In this example, the wirings 161 may interconnect each selected pixel 30a with circuitry in a corresponding one of the quad corner regions 16a, 16b, 16c, 16d of the chip 3, via the openings 32 in the pixel monitoring layer 160, thus enabling the selected pixels 30a to be monitored. In some embodiments, sparse pixel-sensing may be used advantageously to provide flexibility in determining which pixels 30 of the wells 3 of a multi- well system 1 to be monitored, by allowing for the post-fabrication processing of the wells 3 to form and lithographically pattern the pixel monitoring layer 160 with openings 32 over the selected pixels 30a, and to form and pattern an interconnection layer for contacting the selected pixels 30a.

[0096] Having thus described several aspects and embodiments of the present technology, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the disclosure. Further, though advantages of the present disclosure are indicated, it should be appreciated that not every embodiment of the technology described herein will include every described advantage. Some embodiments may not implement any feature(s) described as advantageous herein and in some instances one or more of the described features may be implemented to achieve further embodiments. Accordingly, the foregoing description and drawings are by way of example only.

[0097] Various aspects of the present disclosure may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in connection with one embodiment may be combined in any manner with aspects described in connection with one or more other embodiments.

[0098] Also, the present disclosure may be embodied as one or more method(s) in which various embodiments of the structures described above may be used. The acts performed as part of the one or more method(s) may be ordered in any suitable way.

[0099] Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

[0100] The terms “approximately” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and yet within ±2% of a target value in some embodiments. The terms “approximately” and “about” may include the target value.