Title:
D6T IN-MEMORY COMPUTING ACCELERATOR CAPABLE OF ALWAYS LINEARLY DISCHARGING AND REDUCING NUMERIC STEPS
Document Type and Number:
WIPO Patent Application WO/2024/082377
Kind Code:
A1
Abstract:
Disclosed in the present invention is a D6T in-memory computing accelerator capable of always linearly discharging and reducing numeric steps. In the in-memory computing accelerator disclosed in the present invention, three effective technologies are provided: (1) a decoupled 6T(D6T) bit unit, which can reliably operate at 0.4 V and be standby at 0.26 V, and supports parallel processing of decoupled dual ports; and (2) an always linear discharging convolution mechanism (ALDCM), which not only can reduce the voltage of a bit line, but also can always keep linear computing within the whole voltage range of the bit line; and (3) a bypass of a bias voltage time converter (BVTC), which reduces numeric steps while still maintaining high energy efficiency and computational density at low voltages. A measurement result of the in-memory computing accelerator displays that the average energy efficiency thereof is 8918 TOPS/W(8b×8b), and the average calculation density of a 55 nm CMOS process is 38.6 TOPS/mm 2(8b×8b).
Inventors:
ZHANG HONGTU (CN)
SHU YUHAO (CN)
HA YAJUN (CN)
SHU YUHAO (CN)
HA YAJUN (CN)
Application Number:
PCT/CN2022/134240
Publication Date:
April 25, 2024
Filing Date:
November 25, 2022
Export Citation:
Assignee:
UNIV SHANGHAI TECH (CN)
International Classes:
G06F7/544; G06N3/063
Foreign References:
| CN113935479A | 2022-01-14 | |||
| CN113035251A | 2021-06-25 | |||
| CN111816231A | 2020-10-23 | |||
| US20190370640A1 | 2019-12-05 | |||
| US20210266000A1 | 2021-08-26 |
Attorney, Agent or Firm:
SHANGHAI SHENHUI PATENT AGENT CO., LTD. (CN)
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