TECHNICAL FIELD

The present disclosure relates to a converter circuit. The term “power converter” may be used as a synonym for the term “converter”. Thus, the converter circuit may be referred to as “power converter circuit”. In the present disclosure, the terms “power” and “electrical power” are used as synonyms.

BACKGROUND

Converters are used in power electronics for power conversion. A converter may convert a first power into a second power. For example, a converter may convert an AC power into a DC power. In this case, the converter is an AC-to-DC converter. A converter may convert a DC power into another DC power. In this case, the converter is a DC-to-DC converter.

SUMMARY

Due to the increased power demand of microprocessors, front-end AC-to-DC server power supplies and DC-to-DC server power supplies are desired comprising: very -high power densities and efficiencies; multiple inputs, for redundancy purposes; galvanic isolation between the ports of the power supply; and/or hold-up time capability.

In view of the above, this disclosure aims to provide a converter circuit that allows providing AC-to-DC power supplies and/or DC-to-DC power supplies. An objective of this disclosure is to provide a converter circuit that achieves at least one of the above- mentioned characteristics of AC-to-DC power supplies and DC-to-DC power supplies.

These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims. An aspect of this disclosure provides a converter circuit. The converter circuit comprises n input ports; an output port; n three port converters (TPCs) each having a first port, a second port, and a third port; and m further converters each having two or three ports; wherein n is an integer number equal to or greater than two (n > 2) and m is an integer number equal to or greater than one (m > 1). The first port of each TPC of the n TPCs is electrically connected to a respective input port of the n input ports. A parallel connection of the second port of each TPC of the n TPCs is electrically connected to the output port. The third port of each TPC of the n TPCs is electrically connected to a first port of the two or three ports of each of the m further converters. A second port of the two or three ports of each of the m further converters is electrically connected to an input port of the n input ports or the output port.

The converter circuit may be referred to as multiple-input converter circuit.

The term “power converter” may be used as synonym for the term “converter”. Thus, the terms “two port power converter” and “three port power converter” may be used as synonym for the terms “two port converter” and “three port converter”, respectively.

The converter circuit may be used as a power supply circuit, i.e. power supply. Therefore, the converter circuit may be also referred to as multiple-input power supply circuit or multiple-input power supply. Depending on the type of n TPCs and optionally m further converters the converter circuit may be a multiple-input DC-to-DC power supply (circuit) or an multiple-input AC-to-DC power supply (circuit).

In other words, the aspect of this disclosure proposes to implement a multiple-input power supply (e.g. a multiple-input DC-to-DC power supply or multiple-input AC-to-DC power supply) combining two or more three port converters (TPCs) and one or more further converters having two or three ports. The m further converters may be referred to as m partial power converters (PPCs).

The converter circuit allows achieving an efficient and compact multiple-input isolated power supply for applications requiring hold-up time. The arrangement of the n TPCs and the m further converters allows the TPCs processing a majority of a total power providable to the n input ports of the converter circuits and the m further converters processing a fraction or portion of the total power for controlling, optionally regulating, a voltage (output voltage) providable at the output port of the converter (when the total power is provided to the n input ports).

The m further converters may control, optionally regulate, the output voltage providable by the output port of the converter circuit. In the following, the voltage (i.e. output voltage) providable by the output port of the converter circuit is referred to as “output voltage”. Since the m further converters may be used to control, optionally regulate, the output voltage, the n TPCs may be operated at optimal conditions (i.e. constant switching frequencies) and process a majority of a total power providable to the n input ports of the converter circuit. This results in better overall efficiencies and simplified control schemes.

In case of DC inputs (e.g. the converter circuit being a DC-to-DC converter circuit), i.e. DC powers (e.g. DC input voltages) being provided to the n input ports of the converter circuit, a larger amount of energy from input buffer capacitors of the n TPCs may be used during a hold-up time of the converter circuit, because the m further converters may control, optionally regulate, the output voltage (i.e. the voltages over the input buffer capacitors of the n TPCs are allowed to decrease to much lower values compared to conventional cases since they do not control the output voltage). Therefore, the converter circuit has less energy overhead, which allows smaller buffer capacitors to be used in the n TPCs.

Since the arrangement of the m further converters and the n TPCs allows only a portion or fraction (i.e. small portion/fraction) of the power to be processed by the m further converters (during operation of the converter circuit), the m further converters may be optimized for power density and be operated at higher switching frequencies than the n TPCs. This allows reducing the size of the m further converters, increasing the bandwidth of an output voltage controller for controlling operation of the converter circuit and reducing voltage ripples at the output port or the n input ports of the converter circuit (depending on the electrical connection of the second port of the two or three ports of each of the m further converters). In case of AC inputs (e.g. the converter circuit being an AC-to-DC converter circuit), i.e. AC powers (e.g. AC input voltages) being provided to the n input ports of the converter circuit, an optional capacitor, which may optionally be electrically connected in parallel to the third port of each TPC of the n TPCs, may be used to provide the energy used during a hold-up time of the converter circuit (i.e. during an operation of the converter circuit). The converter circuit may comprise the aforementioned capacitor, in case no capacitor is present in or at the third port of the n TPCs (i.e. in case the n TPCs do not comprise in or at the third port a capacitor). The optional capacitor may be referred to as common bus capacitor. The optional arrangement of the converter circuit comprising the further converter and the n TPCs allows the optional capacitor (optional common bus capacitor) to be shared by all converters. This allows reducing the size of the converter circuit.

The converter circuit comprising the m further converters and the n TPCs allows using direct AC-to-DC converters for implementing the n TPCs in case the converter circuit is desired to be used in applications requiring hold-up time capabilities. This allows reducing the overall size of the converter circuit.

The n TPCs and the m further converters each may be understood as a converter being an actively switched converter or comprising one or more actively switched converters. That is, a TPC or a further converter comprises one or more switches for controlling the function (i.e. conversion of input power(s) to output power(s)) of the respective converter. The TPC may comprise one or more passive components, such as inductor(s) and/or capacitor(s), electrically connected in series and/or in parallel to any of its terminals for supporting or achieving a power conversion and/or filtering. The function of the TPC or the further converter may be a DC-to-DC conversion (i.e. converting input DC power(s) to output DC power(s)) or a AC-to-DC conversion (i.e. converting input AC power(s) to output AC power(s)). The one or more switches of a respective converter may be one or more transistors, such as one or more field effect transistors (FETs), e.g. one or more metal-oxide semiconductor FETs; one or more bipolar junction transistors (BJTs); one or more insulated gate bipolar transistors (IGBTs) etc.

A TPC may be implemented by three two port converters, i.e. three converters each having two ports. The three two port converters each may be understood as a converter comprising or being an actively switched converter. Optionally, a first two port converter of the TPC associated with the first port of the TPC is galvanically isolated from a second two port converter of the TPC associated with the second port of the TPC and a third two port converter of the TPC associated with the third port of the TPC. Optionally, the three two port converters may be galvanically isolated from each other.

The first converter of the TPC may be a DC-to-AC converter and the second and third converters of the TPC may each be an AC -to DC converter. Thus, the first port, second port and third port of the TPC may each be a DC-port. In this case, the TPC may be a DC-to-DC converter. Alternatively, the first converter of the TPC may be an AC-to-AC converter and the second and third converters of the TPC may each be an AC-to-DC converter. Thus, the first port of the TPC may be an AC-port and the second port and third port of the TPC may each be a DC-port. In this case, the TPC may be an AC-to-DC converter. The n TPCs may be galvanically isolated converters. A galvanically isolated converter may be understood as a converter comprising a galvanic isolation between its input port(s) and its output port(s).

For implementing the converters, i.e. the n TPCs (e.g. the three converters of the TPCs) and the m further converters, of the converter circuit any known actively switched converters (e.g. DC-to-DC converter(s), AC-to-DC converter(s) and/or AC-to-AC converter(s)) and/or any known passively switched converters (e.g. AC-to-DC converter(s) with diodes) may be used.

The m further converters may be configured to control, optionally regulate, the voltage (i.e. output voltage) providable by the output port of the converter circuit.

Since the first port of each TPC of the n TPCs is electrically connected to a respective input port of the n input ports, the first ports of the n TPCs may serve as an input (i.e. as n input ports) of the converter circuit.

The converter circuit may be used or employed in any application for which highly efficient power conversion from multiple input ports is desired. Further, the converter circuit may be used or employed in any application for which galvanic isolation is desired and/or at least one of the following are desired specifications: high power density and hold-up time capability. Examples of such applications comprise server power supplies, uninterruptible power supply (UPS) systems, renewable energy systems, battery chargers for electric vehicle (EV), microgrids etc. Thus, the converter circuit may be part of any one of the aforementioned examples.

Optionally, the converter circuit may be employed or used in three-phase systems. The converter circuit may comprise multiple output ports.

In an implementation form of the aspect, the integer number m equals to one (m = 1) and the further converter has the two ports. The third port of each TPC of the n TPCs may be electrically connected to the first port of the two ports of the further converter; and the second port of the two ports of the further converter may be electrically connected to the output port.

This implementation form has the advantage that the further converter may directly control, optionally regulate, the output voltage providable by the output port of the converter circuit. In addition or alternatively, the further converter may function as a power pulsation buffer to reduce output voltage ripples (i.e. ripples of the output voltage providable by the output port of the converter circuit).

The further converter may be configured to control, optionally regulate, the voltage (i.e. output voltage) providable by the output port of the converter circuit.

Since the further converter may be used to control, optionally regulate, the output voltage, the n TPCs may be operated at optimal conditions (i.e. constant switching frequencies) and process a majority of a total power providable to the n input ports of the converter circuit. This results in better overall efficiencies and simplified control schemes.

In case of DC inputs (e.g. the converter circuit being a DC-to-DC converter circuit), i.e. DC powers (e.g. DC input voltages) being provided to the n input ports of the converter circuit, a larger amount of energy from input buffer capacitors of the n TPCs may be used during a hold-up time of the converter circuit, because the further converter may control, optionally regulate, the output voltage (i.e. the voltages over the input buffer capacitors of the n TPCs are allowed to decrease to much lower values compared to conventional cases since they do not control the output voltage). Therefore, the converter circuit has less energy overhead, which allows smaller buffer capacitors to be used in the n TPCs.

Since the arrangement of the further converter and the n TPCs allows only a portion or fraction (i.e. small portion/fraction) of the power to be processed by the further converter (during operation of the converter circuit), the further converter may be optimized for power density and be operated at higher switching frequencies than the n TPCs. This allows reducing the size of the further converter, increasing the bandwidth of an output voltage controller for controlling operation of the converter circuit and reducing voltage ripples at the output port of the converter circuit.

In case of AC inputs (e.g. the converter circuit being an AC-to-DC converter circuit), i.e. AC powers (e.g. AC input voltages) being provided to the n input ports of the converter circuit, an optional capacitor, which may optionally be electrically connected in parallel to the third port of each TPC of the n TPCs, may be used to provide the energy used during a hold-up time of the converter circuit (i.e. during an operation of the converter circuit). The converter circuit may comprise the aforementioned capacitor, in case no capacitor is present in or at the third port of the n TPCs (i.e. in case the n TPCs do not comprise in or at the third port a capacitor). The optional capacitor may be referred to as common bus capacitor. The optional arrangement of the converter circuit comprising the further converter and the n TPCs allows the optional capacitor (optional common bus capacitor) to be shared by all converters. This allows reducing the size of the converter circuit.

The converter circuit allows using direct AC-to-DC converters for implementing the n TPCs in case the converter circuit is desired to be used in applications requiring hold-up time capabilities. This allows reducing the overall size of the converter circuit.

In an implementation form of the aspect, the second port of the two ports of the further converter and the parallel connection of the second port of each TPC of the n TPCs are electrically connected in parallel to the output port. In this implementation form, the further converter may be said to be electrically connected in parallel to the output port of the converter circuit. This implementation form allows high output currents providable by the n TPCs at the output port of the converter circuit. In addition or alternatively, this implementation form allows the n TPCs to have current source characteristics (i.e. using TPCs with current source characteristics). In other words, this implementation form allows the converter circuit to deal with high output currents at its output port and/or the n TPCs having current source characteristics.

In an implementation form of the aspect, a series connection of the second port of the two ports of the further converter and the parallel connection of the second port of each TPC of the n TPCs is electrically connected in parallel to the output port. In this implementation form, the further converter may be said to be electrically connected in series to the output port of the converter circuit.

This implementation form allows high output voltages providable by the n TPCs at the output port of the converter circuit. In addition or alternatively, this implementation form allows the n TPCs to have voltage source characteristics (i.e. using TPCs with voltage source characteristics). In other words, this implementation form allows the converter circuit to deal with high output voltages at its output port and/or the n TPCs having voltage source characteristics.

In an implementation form of the aspect, the integer number m equals to the integer number n (m = n), and the m further converters each have the two ports. The third port of each TPC of the n TPCs may be electrically connected to the first port of the two ports of each of the m further converters; and the second port of the two ports of each of the m further converters may be electrically connected to a respective input port of the n input ports.

This implementation form has the advantage that the m further converters may indirectly control, optionally regulate, the output voltage providable by the output port of the converter circuit (e.g. by controlling, optionally regulating, input voltages providable to the n input ports). In addition or alternatively, the m further converters may function as power pulsation buffers to reduce input voltage ripples (i.e. ripples of input voltages providable to the n input ports of the converter circuit). The m further converters may be configured to indirectly control, optionally regulate, the voltage (i.e. output voltage) providable by the output port of the converter circuit.

Since the m further converters may be used to control, optionally regulate, the output voltage, the n TPCs may be operated at optimal conditions (i.e. constant switching frequencies) and process a majority of a total power providable to the n input ports of the converter circuit. This results in better overall efficiencies and simplified control schemes.

In case of DC inputs (e.g. the converter circuit being a DC-to-DC converter circuit), i.e. DC powers (e.g. DC input voltages) being provided to the n input ports of the converter circuit, a larger amount of energy from input buffer capacitors of the n TPCs may be used during a hold-up time of the converter circuit, because the m further converters may control, optionally regulate, the output voltage (i.e. the voltages over the input buffer capacitors of the n TPCs are allowed to decrease to much lower values compared to conventional cases since they do not control the output voltage). Therefore, the converter circuit has less energy overhead, which allows smaller buffer capacitors to be used in the n TPCs.

Since the arrangement of the m further converters and the n TPCs allows only a portion or fraction (i.e. small portion/fraction) of the power to be processed by the m further converters (during operation of the converter circuit), the m further converters may be optimized for power density and be operated at higher switching frequencies than the n TPCs. This allows reducing the size of the m further converters, increasing the bandwidth of an output voltage controller for controlling operation of the converter circuit and reducing voltage ripples at the n input ports of the converter circuit.

In case of AC inputs (e.g. the converter circuit being an AC-to-DC converter circuit), i.e. AC powers (e.g. AC input voltages) being provided to the n input ports of the converter circuit, an optional capacitor, which may optionally be electrically connected in parallel to the third port of each TPC of the n TPCs, may be used to provide the energy used during a hold-up time of the converter circuit (i.e. during an operation of the converter circuit). The converter circuit may comprise the aforementioned capacitor, in case no capacitor is present in or at the third port of the n TPCs (i.e. in case the n TPCs do not comprise in or at the third port a capacitor). The optional capacitor may be referred to as common bus capacitor. The optional arrangement of the converter circuit comprising the m further converters and the n TPCs allows the optional capacitor (optional common bus capacitor) to be shared by all converters. This allows reducing the size of the converter circuit.

The converter circuit allows using direct AC-to-DC converters for implementing the n TPCs in case the converter circuit is desired to be used in applications requiring hold-up time capabilities. This allows reducing the overall size of the converter circuit.

The m further converters may be m galvanically isolated converters. A galvanically isolated converter may be understood as a converter comprising a galvanic isolation between its input port(s) and its output port(s).

In an implementation form of the aspect, the first port of each TPC of the n TPCs is electrically connected in series with the second port of a respective further converter of the m further converters. Each series connection of the first port of the respective TPC and the second port of the respective further converter may be electrically connected in parallel to a respective input port of the n input ports. In this implementation form, the m further converters may be said to be electrically connected in series to the n input ports of the converter circuit.

This implementation form allows controlling, optionally regulating, input voltages providable to the n input ports of the converter circuit and, thus, the voltages across the first port of each TPC of the n TPCs. This allows reducing voltage ripples at the n input ports of the converter circuit (i.e. at the input side of the converter circuit) and/or indirectly controlling, optionally regulating, the output voltage of the converter circuit.

In an implementation form of the aspect, the first port of each TPC of the n TPCs is electrically connected in parallel with the second port of a respective further converter of the m further converters and a respective input port of the n input ports. In this implementation form, the m further converters may be said to be electrically connected in parallel to the n input ports of the converter circuit. This implementation form allows controlling, optionally regulating, input currents providable or injectable to the n input ports of the converter circuit and, thus, a respective input current providable or injectable to the first port of each TPC of the n TPCs. This allows reducing voltage ripples at the n input ports of the converter circuit (i.e. at the input side of the converter circuit) and/or indirectly controlling, optionally regulating, the output voltage of the converter circuit.

In an implementation form of the aspect, the integer number n is an even integer number, the integer number m equals to half the integer number n (m = n/2), and the m further converters each have the three ports. The third port of each TPC of the n TPCs may be electrically connected to the first port of the three ports of each of the m further converters. The second port and a third port of the three ports of each of the m further converters may be each electrically connected to a respective input port of the n input ports.

This implementation form has the advantage that the m further converters may indirectly control, optionally regulate, the output voltage providable by the output port of the converter circuit (e.g. by controlling, optionally regulating, input voltages providable to the n input ports). In addition or alternatively, the m further converters may function as power pulsation buffers to reduce input voltage ripples (i.e. ripples of input voltages providable to the n input ports of the converter circuit). The implementation form, where the integer number m is equal to half the integer number n (m = n/2) achieves the same advantages as the implementation form, where the integer number m is equal to the integer number n (m = n). Compared to the implementation form, where the integer number m equals to the integer number n (m = n), using m further converters each having three ports with m being half the integer number n (m = n/2) allows reducing a number of employed magnetic components used for implementing the converter circuit. The m further converters may be m galvanically isolated converters.

In an implementation form of the aspect, the first port of each TPC of a first half of the n TPCs is electrically connected in series with the second port of a respective further converter of the m further converters. Each series connection of the first port of the respective TPC of the first half of the n TPCs and the second port of the respective further converter may be electrically connected in parallel to a respective input port of a first half of the n input ports. The first port of each TPC of a second half of the n TPCs may be electrically connected in series with the third port of a respective further converter of the m further converters. Each series connection of the respective first port of the respective TPC of the second half of the n TPCs and the third port of the respective further converter may be electrically connected in parallel to a respective input port of a second half of the n input ports. In this implementation form, the m further converters may be said to be electrically connected in series to the n input ports of the converter circuit.

This implementation form allows controlling, optionally regulating, input voltages providable to the n input ports of the converter circuit and, thus, the voltages across the first port of each TPC of the n TPCs. This allows reducing voltage ripples at the n input ports of the converter circuit (i.e. at the input side of the converter circuit) and/or controlling, optionally regulating, the output voltage of the converter circuit.

In an implementation form of the aspect, the first port of each TPC of a first half of the n TPCs is electrically connected in parallel with the second port of a respective further converter of the m further converters and a respective input port of a first half of the n input ports. The first port of each TPC of a second half of the n TPCs may be electrically connected in parallel with the third port of a respective further converter of the m further converters and a respective input port of a second half of the n input ports. In this implementation form, the m further converters may be said to be electrically connected in parallel to the n input ports of the converter circuit.

This implementation form allows controlling, optionally regulating, input currents providable or injectable to the n input ports of the converter circuit and, thus, a respective input current providable or injectable to the first port of each TPC of the n TPCs. This allows reducing voltage ripples at the n input ports of the converter circuit (i.e. at the input side of the converter circuit) and/or controlling, optionally regulating, the output voltage of the converter circuit.

In an implementation form of the aspect, the converter circuit comprises a capacitor electrically connected in parallel to the third port of each TPC of the n TPCs. The optional capacitor may be referred to as common bus capacitor. The optional capacitor may be a common DC link capacitor. The optional capacitor allows storing energy used during a hold-up time of the converter circuit (i.e. during an operation of the converter circuit). The converter circuit may comprise the aforementioned capacitor, in case no capacitor is present in or at the third port of the n TPCs (i.e. in case the n TPCs do not comprise in or at the third port a capacitor).

In an implementation form of the aspect, the n TPCs are each configured to receive a first DC power at the first port and provide, using the first DC power, a second DC power at the second port and a third DC power at the third port. Alternatively, the n TPCs may be each configured to receive an AC power at the first port and provide, using the AC power, a first DC power at the second port and a second DC power at the third port.

In other words, the first port, second port and third port of a TPC may each be a DC-port. Alternatively, the first port of a TPC may be an AC-port and the second port and third port of the TPC may each be a DC-port.

A TPC configured to receive a first DC power at the first port and provide, using the first DC power, a second DC power at the second port and a third DC power at the third port may be referred to as “DC-DC-DC TPC”. For this, the TPC may be implemented by three two port converters, wherein a first two port converter associated with the first port may be a DC-to-AC converter (with the DC side connected to the first port). A second two port converter associated with the second port of the TPC and a third two port converter associated with the third port of the TPC each may be an AC-to-DC converter (with the DC side connected to the second port respectively third port). The first two port converter may be galvanically isolated from the second two port converter and the third two port converter. Optionally, the three two port converters may be galvanically isolated from each other.

A TPC configured to receive an AC power at the first port and provide, using the AC power, a first DC power at the second port and a second DC power at the third port may be referred to as “AC-DC-DC TPC”. For this, the TPC may be implemented by three two port converters, wherein a first two port converter associated with the first port may be an AC-to-AC converter. A second two port converter associated with the second port of the TPC and a third two port converter associated with the third port of the TPC each may be an AC-to-DC converter (with the DC side connected to the second port respectively third port). The first two port converter may be galvanically isolated from the second two port converter and the third two port converter. Optionally, the three two port converters may be galvanically isolated from each other.

In an implementation form of the aspect, the further converter is a DC-to-DC converter.

In an implementation form of the aspect, the m further converters are each an AC-to-DC converter or an DC-to-DC converter. The m further converters (e.g. the AC-to-DC converters or DC-to-DC converters) may be galvanically isolated converters.

In an implementation form of the aspect, the m further converters are each configured to receive a first DC power at the second port and a second DC power at the third port, and provide, using the first DC power and the second DC power, a third DC power at the first port. Alternatively, the m further converters may be each configured to receive a first AC power at the second port and a second AC power at the third port, and provide, using the first AC power and the second AC power, a DC power at the first port.

In other words, the first port, second port and third port of a further converter may each be a DC-port. Alternatively, the second port and third port of a further converter may each be an AC-port and the first port of the further converter may be a DC-port.

For the aforementioned first alternative of implementing the m further converters, a further converter may be implemented by three two port converters, wherein a first two port converter associated with the second port of the further converter and a second two port converter associated with the third port of the further converter each may be an DC- to-AC converter (with the DC side connected to the second port respectively third port). A third two port converter associated with the first port of the further converter may be an AC-to-DC converter (with the DC side connected to the first port). The first two port converter and second two port converter may be galvanically isolated from the third two port converter. Optionally, the three two port converters may be galvanically isolated from each other. For the aforementioned second alternative of implementing the m further converters, a further converter may be implemented by three two port converters, wherein a first two port converter associated with the second port of the further converter and a second two port converter associated with the third port of the further converter each may be an AC- to-AC converter. A third two port converter associated with the first port of the further converter may be an AC-to-DC converter (with the DC side connected to the first port). The first two port converter and second two port converter may be galvanically isolated from the third two port converter. Optionally, the three two port converters may be galvanically isolated from each other.

In an implementation form of the aspect, the converter circuit is an AC-to-DC converter circuit or a DC-to-DC converter circuit.

In order to achieve the converter circuit according to the aspect of this disclosure, some or all of the implementation forms and optional features of the aspect, as described above, may be combined with each other.

All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspect and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Figure 1 shows an example of a converter circuit according to an embodiment of this disclosure; Figure 2 shows an example of a three port converter (TPC) according to an embodiment of this disclosure; and

Figures 3 to 9 each show an example of a converter circuit according to an embodiment of this disclosure.

In the Figures, corresponding elements are labeled with the same reference sign.

DETAILED DESCRIPTION OF EMBODIMENTS

Figure 1 shows an example of a converter circuit according to an embodiment of this disclosure. The converter circuit of Figure 1 is an example of the converter circuit according to the aspect of this disclosure, as described above. The above description of the converter circuit according to the aspect of this disclosure is correspondingly valid for the converter circuit of Figure 1.

The converter circuit 1 of Figure 1 comprises two input ports INI and IN2; an output port OUT; two three port converters 2 (TPCs) each having a first port 21, a second port 22, and a third port 23; and a further converter 3 having two ports 31 and 32. The number of input ports and TPCs shown in Figure 1 is only by way of example not limiting this disclosure. Thus, the converter circuit 1 may have n input ports and n TPCs 2, wherein n is an integer number equal to or greater than two (n > 2). The number of further converter shown in Figure 1 is only by way of example and not limiting this disclosure. Thus, the converter circuit 1 may have m further converters, wherein m is an integer number equal to or greater than one (m > 1). According to Figure 1, the further converter 3 has two ports 31 and 32. According to another example, not shown in Figure 1, the m further converters 3 may have three ports (this is exemplarily shown in Figures 8 and 9). The following description is correspondingly valid for a different number of input ports, TPCs 2 and/or further converter 3 as the one shown in Figure 1. The following description is correspondingly valid for the case that the further converter(s) 3 comprises three ports.

As shown in Figure 1, the first port 21 of each TPC 2 is electrically connected to a respective input port of the input ports INI and IN2. A parallel connection of the second port 22 of each TPC 2 is electrically connected to the output port OUT. The third port 23 of each TPC 2 is electrically connected to a first port 31 of the ports 31 and 32 of the further converter 3. A second port 32 of the ports 31 and 32 of the further converter 3 is electrically connected to the output port OUT. Alternatively, the further converter 3 (which may be differently implemented) may be electrically connected to the two input ports INI and IN2 of the converter circuit 1 (as exemplarily indicated in Figures 8 and 9). The TPCs 2 may be DC-DC-DC TPCs or AC-DC-DC TPCs, as indicated in Figure 1.

Figure 2 shows an example of a three port converter (TPC) according to an embodiment of this disclosure. Figure 2 shows an example of an implementation of a TPC that may be used in the converter circuit of any one of Figures 1 and 3 to 9.

As shown in Figure 2, the TPC 2 may be a DC-DC-DC TPC or an AC-DC-DC TPC, wherein the AC side is associated with the first port 21 (i.e. the first port 21 is an AC- port).

As shown at the bottom of Figure 2, for implementing the TPC 2 the TPC may comprise three two port converters 2a. 2b and 2c. A first two port converter 2a of the TPC 2 associated with the first port 21 of the TPC 2 may be galvanically isolated from a second converter 2b of the TPC 2 associated with the second port 22 of the TPC 2 and a third converter 2c of the TPC 2 associated with the third port 23 of the TPC 2. Optionally, the three two port converters 2a, 2b and 2c may be galvanically isolated from each other.

The first converter 2a of the TPC 2 may be a DC-to-AC converter and the second and third converters 2b and 2c of the TPC 2 may each be an AC -to DC converter. In this case, the TPC 2 may be a DC-to-DC converter (i.e. the first port 21, second port 22 and third port 23 of the TPC 2 may each be a DC-port). Alternatively, as shown in Figure 2, the first converter 2a of the TPC 2 may be an AC-to-AC converter and the second and third converters 2b and 2c of the TPC 2 may each be an AC -to DC converter. In this case, the TPC may be an AC-to-DC converter (i.e. the first port 21 of the TPC 2 may be an AC- port and the second port 22 and third port 23 of the TPC 2 may each be a DC-port).

Figures 3 to 9 each show an example of a converter circuit according to an embodiment of this disclosure. The converter circuits of Figures 3 to 9 are examples of the converter circuit according to the aspect of this disclosure, as described above. The above description of the converter circuit according to the aspect of this disclosure is correspondingly valid for the converter circuits of Figures 3 to 9.

The converter circuit of Figure 3 corresponds to the converter circuit of Figure 1 comprising an additional feature. Thus, the description of Figure 1 is correspondingly valid for the converter circuit of Figure 3 and in the following mainly the additional feature is described. As shown in Figure 3, the converter circuit 1 comprises a capacitor 4 electrically connected in parallel to the third port 23 of each TPC 2. The capacitor 4 may be present irrespective of the number of input ports, TPCs 2 and/or further converter 3. The optional capacitor 4 may be referred to as common bus capacitor. The optional capacitor 4 may be a common DC link capacitor. The optional capacitor 4 allows storing energy used during a hold-up time of the converter circuit 1 (i.e. during an operation of the converter circuit 1). The optional capacitor 4 may be present in each of the converter circuits of Figures 4 to 9.

With regard to the Figures, the number of input ports, TPCs 2 and/or further converter(s) 3 is only by way of example and does not limit this disclosure.

The converter circuit 1 of Figure 4 comprises n input ports INI, IN2, ... , INn; an output port OUT; n three port converters 2 (TPCs) each having a first port 21, a second port 22, and a third port 23; and a further converter 3 having two ports 31 and 32; wherein n is an integer number equal to or greater than two (n > 2). In Figure 4, exemplarily three input ports and three TPCs are shown. The converter circuit 1 of Figure 4 comprises m further converter 3, wherein m is an integer number equalling to one (m = 1). As shown in Figure 4, the first port 21 of each TPC of the n TPCs 2 is electrically connected to a respective input port of the n input ports INI, IN2, ... , INn. A parallel connection of the second port 22 of each TPC of the n TPCs 2 is electrically connected to the output port OUT of the converter circuit 1. The third port 23 of each TPC of the n TPCs 2 is electrically connected to a first port 31 of the two ports 31 and 32 of the further converter 3. A second port 32 of the two ports 31 and 32 of the further converter 3 is electrically connected to the output port OUT. As shown in Figure 4, a series connection of the second port 32 of the two ports 31 and 32 of the further converter 3 and the parallel connection of the second port 22 of each TPC of the n TPCs 2 (i.e. the parallel connection of the second ports 22 of the n TPCs 2) may be electrically connected in parallel to the output port OUT. In this case, the further converter 3 may be said to be connected in series to the output port OUT.

Alternatively, the second port 32 of the two ports 31 and 32 of the further converter 3 and the parallel connection of the second port 22 of each TPC of the n TPCs 2 may be electrically connected in parallel to the output port. In this case, the further converter 3 may be said to be connected in parallel to the output port OUT. This alternative is shown in Figure 5. Thus, the description of Figure 4 may be correspondingly valid for the converter circuit 1 of Figure 5.

The converter circuit 1 of Figure 6 comprises n input ports INI, IN2, ... , INn; an output port OUT; n three port converters 2 (TPCs) each having a first port 21, a second port 22, and a third port 23; and m further converters 3 each having two ports 31 and 32; wherein n is an integer number equal to or greater than two (n > 2) and m is an integer number equaling to the integer number n (m = n). In Figure 6, exemplarily three input ports, three TPCs and three further converters are shown. As shown in Figure 6, the first port 21 of each TPC of the n TPCs 2 is electrically connected to a respective input port of the n input ports INI, IN2, ... , INn. A parallel connection of the second port 22 of each TPC of the n TPCs 2 is electrically connected to the output port OUT. The third port 23 of each TPC of the n TPCs 2 is electrically connected to a first port 31 of the two ports 31 and 32 of each of the m further converters 3 (m = n). A second port 32 of the two ports 31 and 32 of each of the m further converters 3 (m = n) is electrically connected to a respective input port of the n input ports INI, IN2, ... , INn.

As shown in Figure 6, the first port 21 of each TPC of the n TPCs 2 may be electrically connected in parallel with the second port 32 of a respective further converter of the m further converters 3 and a respective input port of the n input ports INI, IN2, ... ., INn. In this case, the further converters 3 may be said to be connected in parallel to the input ports INI, IN2, ...., INn. Alternatively, the first port 21 of each TPC of the n TPCs 2 may be electrically connected in series with the second port 22 of a respective further converter of the m further converters 3. Each series connection of the first port 21 of the respective TPC 2 and the second port 32 of the respective further converter 3 may be electrically connected in parallel to a respective input port of the n input ports INI, IN2, ... , INn. In this case, the further converters 3 may be said to be connected in series to the input ports INI, IN2, ... INn. This alternative is shown in Figure 7. Thus, the description of Figure 6 may be correspondingly valid for the converter circuit 1 of Figure 7.

The converter circuit 1 of Figure 8 comprises n input ports INI, IN2, ... , INn; an output port OUT; n three port converters 2 (TPCs) each having a first port 21, a second port 22, and a third port 23; and m further converters 3 each having three ports 31, 32 and 33; wherein n is an even integer number equal to or greater than two (n > 2) and m is an integer number equalling to half the integer number n (m = n/2). In Figure 8, exemplarily four input ports, four TPCs and two further converters are shown. As shown in Figure 8, the first port 21 of each TPC of the n TPCs 2 is electrically connected to a respective input port of the n input ports INI, IN2, ... , INn. A parallel connection of the second port 22 of each TPC of the n TPCs 2 is electrically connected to the output port OUT. The third port 23 of each TPC of the n TPCs 2 is electrically connected to a first port 31 of the three ports 31, 32 and 33 of each of the m further converters 3 (m = n/2). A second port 32 and a third port 33 of the three ports 31, 32 and 33 of each of the m further converters 3 (m = n/2) may be each electrically connected to a respective input port of the n input ports INI, IN2, ... , INn.

As shown in Figure 8, the first port 21 of each TPC of a first half of the n TPCs 2 may be electrically connected in parallel with the second port 32 of a respective further converter of the m further converters 3 and a respective input port of a first half of the n input ports INI, IN2, ... , INn. The first port 21 of each TPC of a second half of the n TPCs 2 may be electrically connected in parallel with the third port 33 of a respective further converter of the m further converters 3 and a respective input port of a second half of the n input ports INI, IN2, ... , INn. In this case, the further converters 3 may be said to be connected in parallel to the input ports INI, IN2, ... ., INn. Alternatively, the first port 21 of each TPC of a first half of the n TPCs 2 may be electrically connected in series with the second port 32 of a respective further converter of the m further converters 3 (m = n/2). Each series connection of the first port 21 of the respective TPC of the first half of the n TPCs 2 and the second port 32 of the respective further converter may be electrically connected in parallel to a respective input port of a first half of the n input ports INI, IN2, ... , INn. The first port 21 of each TPC of a second half of the n TPCs 2 may be electrically connected in series with the third port 33 of a respective further converter of the m further converters 3 (m = n/2). Each series connection of the respective first port 21 of the respective TPC of the second half of the n TPCs 2 and the third port 33 of the respective further converter may be electrically connected in parallel to a respective input port of a second half of the n input ports INI, IN2, ... , INn. In this case, the further converters 3 may be said to be connected in series to the input ports INI, IN2, ...., INn. This alternative is shown in Figure 9. Thus, the description of Figure 8 may be correspondingly valid for the converter circuit 1 of Figure 9.

For further details on the circuits of Figures 1 to 9 reference is made to the description of the converter circuit according to the aspect of this disclosure.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.