Title:
CLOCK GENERATION CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/077800
Kind Code:
A1
Abstract:
Provided in the present disclosure are a clock generation circuit and a memory. The clock generation circuit comprises: a sampling module, which samples continuous chip selection signals on the basis of a sampling clock to acquire odd data and even data; a detection module, which outputs an indication signal of a first state when detecting adjacent chip selection signals satisfy a preset condition, and otherwise, outputs an indication signal of a second state, the preset condition comprising that the data bits of the previous chip selection signal are in a first level state, and the first data bit of the next chip selection signal is in a second level state; and a generation module, which is used for generating an output clock when the indication signal is in a first state. The present solution can generate an output clock in time while ensuring accurate and reliable sampling.
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Inventors:
TANG YULING (CN)
WANG LIN (CN)
WANG LIN (CN)
Application Number:
PCT/CN2023/070338
Publication Date:
April 18, 2024
Filing Date:
January 04, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/12
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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