Title:
I/O CIRCUIT, SEMICONDUCTOR DEVICE, CELL LIBRARY, AND METHOD FOR DESIGNING CIRCUIT OF SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/057763
Kind Code:
A1
Abstract:
This I/O circuit 10 is formed by discretionarily combining a plurality of types of standard cells included in a cell library 100. A standard cell 150 included in the plurality of types of standard cells includes: a first element formation region 151 configured such that a first protection element P11 connected between a signal line and a power supply line and a second protection element N11 connected between the signal line and a ground line are formed; and a second element formation region 152 configured such that a third protection element N12 connected between the power supply line and the ground line is formed. Both the second protection element N11 and the third protection element N12 are formed in a common well.
Inventors:
YAMAOKA SHUNTA (JP)
Application Number:
PCT/JP2023/028414
Publication Date:
March 21, 2024
Filing Date:
August 03, 2023
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
H01L27/04; H01L21/822; H01L21/8234; H01L27/06
Foreign References:
| JP2009206402A | 2009-09-10 | |||
| JP2022105405A | 2022-07-14 | |||
| JP2009164195A | 2009-07-23 | |||
| JP2010080622A | 2010-04-08 | |||
| JP2002050698A | 2002-02-15 | |||
| JPH11251453A | 1999-09-17 |
Attorney, Agent or Firm:
SANO PATENT OFFICE (JP)
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