AVALANCHE DIODE ARRANGEMENT

BACKGROUND

Single photon avalanche diodes ( SPADs ) are increasingly employed in a wide range of applications . For example , an SPAD may be used to detect a point of time , when a photon hits an optical device .

Generally, the SPAD works in a so-called Geiger mode . In the Geiger mode , the SPAD is reverse biased with a bias voltage higher than a breakdown voltage of the avalanche diode . When the photon hits the SPAD, an electron-hole pair is generated . Due to the very high electrical field, a very high short current pulse is generated . The carriers are accelerated by the high electric field until they impact ionize , thus generating additional carrier pairs . Accordingly, a positive feedback loop is established, causing the current to swiftly rise to its final value . Accordingly, once triggered, the avalanche final current keeps on flowing . Quenching circuits have been developed which are configured to bring the device back into its original state . Active quenching circuits are operable to detect the avalanche and then control the bias voltage of the avalanche diode .

It is an obj ect of the present invention to provide an improved avalanche diode arrangement and an improved method of driving the avalanche diode arrangement .

SUMMARY

According to embodiments , the above obj ect is achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

According to embodiments , an avalanche diode arrangement comprises an avalanche diode including an anode connected to first voltage terminal and a cathode connected to a first node . The first node is connected to a first terminal of a quench transistor via a first PMOS transistor . The first PMOS transistor forms part of a level shifting circuit . A second terminal of the quench transistor is connected to a second voltage terminal . Accordingly, the level shifting circuit is merged with the quench transistor . Due to this configuration, area is saved . The avalanche diode may be a single photon avalanche diode ( SPAD) .

For example , the first node is further connected to a gate electrode of a second PMOS enhancement type transistor of the level shifting circuit .

For example , the level shifting circuit further comprises a gating transistor configured to pull the first node to a ground potential . Due to this configuration, it is possible to operate the avalanche diode arrangement in a new operation mode , as will be explained below in more detail .

The avalanche diode arrangement may further comprise a core circuit for supplying voltages to gate electrodes of a first and a second NMOS , respectively, the first and the second NMOS transistors further forming part of the level shifting circuit . The core circuit is configured to set the voltages to the gate electrodes of the first and the second NMOS transistors to a non-conducting state .

The avalanche diode arrangement may further comprise a transistor implementing a readout buffer, wherein an output of the avalanche diode is connected to a gate electrode of the readout buffer .

According to further embodiments , the avalanche diode arrangement may further comprise a capacitor and a transistor implementing a readout buffer . One terminal of the capacitor is connected to the cathode of the avalanche diode , another terminal of the capacitor is connected to the transistor .

According to embodiments , a sensor comprises the avalanche diode arrangement as explained above . Moreover, an electronic device may comprising this sensor . For example , the electronic device may be implemented as a mobile phone , an imaging device or as smart glasses .

A method of driving an avalanche diode arrangement comprising an avalanche diode may comprise connecting a first node of the avalanche diode arrangement to a second voltage terminal via a first transistor, a cathode of the avalanche diode being connected to the first node , an anode of the avalanche diode being connected to a first voltage terminal . The method may further comprise switching- off the first transistor after a photon has been detected by the avalanche diode .

Further , the method according to claim 10 may comprise switching-on the first transistor to re-connect the first node with the second voltage terminal .

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .

Fig . 1A illustrates an avalanche diode arrangement according to embodiments .

Fig . IB illustrates an avalanche diode arrangement according to further embodiments .

Fig . 2A illustrates a diagram of a measurement . Fig. 2B illustrates a time diagram of a quench operation.

Fig. 3A illustrates a sensor according to embodiments.

Fig. 3B illustrates an electronic device according to embodiments .

Fig. 4 summarizes a method according to embodiments.

DETAILED DESCRIPTION

In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims .

The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

As employed in this specification, the terms "coupled" and/or "electrically coupled" are not meant to mean that the elements must be directly coupled together - intervening elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" may describe a low-ohmic electric connection between the elements electrically connected together. According to further embodiments and where appropriate, the term "electrically connected" may mean that the respective elements are "directly connected" or are "directly and permanently connected".

Fig. 1A illustrates an avalanche diode arrangement 100 according to embodiments. The avalanche diode arrangement 100 comprises an avalanche diode 110 which is implemented as a single photon avalanche diode (SPAD) . An anode 111 of the avalanche diode 110 is connected to a first voltage terminal 115. A cathode 112 of the avalanche diode 110 is connected to a first node 114. The first node 114 is further connected to a first terminal 122 of a quench transistor 121 via a first transistor 125 that may be implemented as an enhancement type PMOS transistor. The first transistor 125 forms part of a level shifting circuit 120. A second terminal 123 of the quench transistor 121 is connected to a second voltage terminal 116.

Avalanche diodes are operated at high voltages. For example, typically a voltages difference larger than e.g. 1.5 V are applied to the terminals of the avalanche diode. Accordingly, the first voltage terminal 115 may be a high voltage terminal. On the other side, the core circuitry for supplying the logic levels to the transistors are operated at low voltage levels, e.g. at voltages less than 1 V, e.g. 0.8 V. Therefore, an avalanche diode arrangement generally comprises a level shifting circuit 120, which is configured to deliver voltage signals at higher levels than the control voltage of transistors employed. For example, the second voltage terminal 116 may be connected to a middle voltage level of approximately 1.5 to 5 V, e.g. 2.5 V.

As illustrated in Fig. 1A, the level shifting circuit 120 may for example comprise a first transistor 125 implemented as an enhancement type PMOS transistor and a second transistor 126 implemented as an enhancement type PMOS transistor. The level shifting circuit 120 further comprises a first transistor 130 implemented as an NMOS transistor and a second transistor 131 implemented as an NMOS transistor. A source terminal of the first

NMOS transistor 130 and of the second NMOS transistor 131 is connected to GND, respectively . The first node 114 is arranged between a drain region of the first PMOS transistor 125 and the drain region of the first NMOS transistor 130 . The first node 114 may be further connected to a gate electrode 127 of the second PMOS transistor 126 . A second node 118 is arranged between the drain region of the second PMOS transistor 126 and the drain region of the second NMOS transistor 131 . The second node 118 is connected to the gate electrode 124 of the first PMOS transistor 125 . A third transistor 135 may be arranged between the first node 114 and the first NMOS transistor 130 . A fourth transistor 136 may be arranged between the second node 118 and the second NMOS transistor 131 . The third and the fourth transistors 135 , 136 are used as cascode transistors to protect the on/off switches , i . e . the first NMOS transistor 130 and the second NMOS transistor 131 .

A first gating node 138 is arranged between the fourth transistor 136 and the second NMOS transistor 131 . A second gating node 139 is arranged between the third NMOS transistor 135 and the first NMOS transistor 130 . A source terminal of the gating transistor 128 is connected to GND . A drain terminal of the gating transistor 128 is connected to the second gating node 139 . The first gating node 138 is connected to a gate electrode of the gating transistor 128 . The gating transistor 128 may be an NMOS transistor .

The quench transistor 121 implements a voltage controlled current source . For example , a gate electrode of the quench transistor 121 is connected to a common bias generator 129 with adj ustable current setting . This allows to adj ust the deadtime of the SPAD .

The quench transistor 121 is connected in series to the on/off switches , i . e . the first PMOS transistor 125 , the third NMOS transistor 135 and the first NMOS transistor 130 . The second NMOS transistor 131 , the fourth NMOS transistor 136 as well as the second PMOS transistor 126 act as a second branch of the level shifting circuit 120 . The second PMOS transistor 126 is further connected to a current source device 119 . The current source device may be implemented as a PMOS transistor . The current source device 119 acts as a load in order to weaken the driving strength of the PMOS path . A source terminal of the PMOS transistor implementing the current source device 119 may be connected to the second voltage terminal 116 .

The avalanche diode arrangement 100 may further comprise a reset transistor 137 which may be implemented as an NMOS transistor . The reset transistor 137 is configured to initialize the level shifting circuit state after ramping up a supply voltage .

The avalanche diode arrangement 100 may further comprise a readout buffer 140 which may be implemented as an enhancement type PMOS transistor . A source terminal of the readout buffer 140 may be connected to the second voltage terminal 116 . The readout buffer 140 is further connected to a constant current source load 145 . The switch between the readout buffer 140 and the current source 145 may be activated in dependence of a signal 16 , i . e . the signal enabling the second NMOS transistor 131 . The avalanche diode arrangement further may comprise a down-level shifting stage 141 for shifting the output voltage level down to a low voltage level and a pulseshaping stage 142 . For example , the pulse-shaping stage may adj ust the pulse width e . g . shorten the pulse width . As a consequence , a plurality of pulses at short time intervals may be distinguished from each other .

The right-hand side of Fig . 1A further illustrates the signal output of a core circuit 105 when corresponding input signals are input . In particular, enable signal 16 is applied to the gate electrodes of the second NMOS transistor 131 . Further , enable signal 17 is applied to the gate electrodes of the first NMOS transistor 130 . The enable signals 16 , 17 are generated in dependence from input signals . Input signal 13 designates a GATING signal , input signal 14 designates a TEST EVENT signal , and input signal 15 designates a SPAD enable signal which indicates whether the avalanche diode arrangement is active . Specific combinations of signals will be explained below with reference to a truth table when discussing operating modes of the avalanche diode arrangement 100 . As is shown in Fig . 1A, the quench transistor 121 which is implemented as a current source is merged with the level shifting circuit 120 . In more detail , the quench transistor 121 is arranged between the second voltage terminal 116 and the first PMOS transistor 125 . As a consequence , area for the avalanche diode arrangement 100 may be reduced . The term "quench circuitry" as used within the present disclosure refers to the combination of the quench transistor 121 and further components of the level shifting circuit 120 .

As is further illustrated in Fig . 1A, due to the arrangement of the quench transistor 121 between the second voltage terminal 116 and the first PMOS transistor 125 and due to the provision of the gating transistor 128 , it is possible to operate the avalanche diode arrangement 100 in a new operating mode , as will be explained in more detail below .

Fig . IB shows an avalanche diode arrangement 100 comprising similar components as the avalanche diode arrangement 100 illustrated in Fig . 1A so that a detailed description thereof is omitted . In contrast to embodiments illustrated in Fig . 1A, the avalanche diode arrangement 100 comprises a capacitor 143 . Accordingly, AC coupling between the readout buffer 140 and the cathode 112 of the avalanche diode 110 is used . A source terminal of the readout buffer 140 may be connected to a low voltage terminal . A signal 17 which is also applied to the gate electrode 132 of the first NMOS transistor 130 is applied to the gate electrode of the readout buffer 140 . Fig . IB further shows an inverter 144 which may form part of the down-level shifting stage 141 . Further, the avalanche diode arrangement 100 may further comprise a pulse-shaping stage 142 . Finally, an output signal 150 is output from the avalanche diode arrangement 100 .

In particular , it is possible to operate the avalanche diode arrangement 100 as explained above with reference to Figs . 1A and IB in the following operation modes : 1. RESET mode: During the RESET mode, the reset transistor 137 is enabled by applying a corresponding reset signal 18 to the gate electrode of the reset transistor 137. Since source terminal of the reset transistor 137 is connected to GND, in the reset mode, the cathode 112 of the avalanche diode 110 is set to GND. Hence, the avalanche diode 110 is disabled and the quench circuitry is initialized as long as the core circuitry 105 is not activated and signals 16 and 17 are not input to the avalanche diode arrangement.

2. OFF mode: During the OFF mode, the reset transistor 137 is switched off. The signal 13 is set to "0" or "1", the signals 14 and 15 are set to "0". Accordingly, 16 is at "0" and signal 17 is at "1". Consequently, node 114 is connected to ground. Accordingly, the cathode 112 is forced to GND. Consequently, the avalanche diode 110 is disabled and the readout buffer 140 is disabled.

3. ON mode (free running) : In this case, the reset transistor 137 is in an off state. The signal 15 is at "1", signal 14 is at "0" and signal 13 is at "0". Accordingly, signal 17 is at "1" and signal 16 is at "0". As a result, the first node 114 is charged via the quench transistor 121 to the voltage supplied by the second voltage terminal 116, e.g. 2.5 V. The readout buffer 140 is active. In this case, the avalanche diode 110 is active and able to detect photons 10.

4. ON mode (gating of latch mode) : In this case, signal 15 is at "1", signal 14 is at "0", and signal 13 is at "1". Accordingly, this mode basically corresponds to the free running ON mode, wherein differing from the free running ON mode, signal 13 is at "1". Consequently, signal 17 is at "0" and signal 16 is at "0". Accordingly, in a similar manner as according to the free running ON mode, the first node 114 is at the supply voltage supplied by the second terminal 116, e.g. 2.5 V. Accordingly, the avalanche diode 110 is active and able to detect photons. The quench circuitry works now in a latch mode. This means that in case no photon arrives , the avalanche diode 110 remains active and does not consume power .

As soon as a photon 10 arrives , the avalanche diode 110 generates electron-hole pairs and pulls down the voltage at the first node 114 . As a result , the level shifting circuit 120 will toggle and disable the quench circuitry . In other words , the quench path comprising the quench transistor 121 and the first transistor 125 is disconnected . As long as the gating signal 13 is at a high level , the signal 16 is at a low level , thus disabling the second NMOS transistor 131 . Hence , the first node 114 is connected to GND via the gating transistor 128 . In particular, the gate electrode of the gating transistor 128 is connected to the second node 118 . Consequently, the quench transistor 121 will not raise the voltage at the first node 114 and the quench circuitry becomes disabled . No further photon will be detected until the GATING signal 13 goes back to "0" to release the quench circuitry 121 , 125 again . Accordingly, the quench circuitry is latched until the GATING signal 13 is changed .

The different operation modes are summarized in the truth table below :

According to the fourth mode , after detection of a photon, the avalanche diode 110 is pulled to an inactive state by setting a low voltage at the first node 114 . Accordingly, one single event is detected, thereafter, the detector is in an idle mode and may be reactivated when the next measurement cycle is started, e . g . by setting the GATING signal 13 to " 0" . Due to this ON mode, which refers to the gating of the latch mode, it is possible to increase the power efficiency of the device.

For example, high resolution direct time-of-f light systems use multiplexing in the time domain to cover the desired measurement distance range with a very limited dynamic range of a TDC (time-to- digital converter) and the histogram memory. For example, for a distance of 10 m, a travel time for the photons amounts to approximately 66 ns. Assuming a histogram bin resolution of 250 ps, the TDC and the histogram memory (HMEM) would require 66 ns/250 ps = 264 stages/counters which is hard to implement on a limited layout area .

Therefore, windowing or multiplexing in the Z-domain is used. Windowing means that the total range is subdivided into submeasurement cycles covering only a limited distance (e.g. 0-1.5 m which corresponds to approximately 10 ns) . In order to cover 1.5 m, a 40 stage TDC and HMEM is sufficient, which may be easily implemented with limited layout area. Due to the reduction of layout area of the avalanche diode arrangement 100 as has been discussed above, this can be implemented in an improved manner.

After a first measurement cycle, the HMEM content is stored outside the focal plane or process using a peak detection algorithm to check whether a peak is present in the data. In a second measurement, the same TDC and HMEM are used to cover 1.5 m to 3 m, in a third 3 m to 4.5 m and so on.

This means, that SPAD events are only processed by the TDC in case they are detected within the current window. For example, if the full range is covered by n = 8 windows, for each measurement only 1/8 of the time SPADs events are detected, while 7/8 of the time SPAD readout may consume power without any benefit.

Fig. 2A illustrates the multiplexing in the Z-domain using the windowing concept . As can be seen from Fig. 2A, in the first measurement cycle (e.g. 0 to 1.5 m) during window 0, photons are detected by the TDC whereas in windows 1 to n no photons are detected. Thereafter, in the second measurement cycle, photons are detected for the window 1 (e.g. 1.5 to 3 m) and no photons are detected for windows 0 and 2 to n. The GATING signal 13 is set correspondingly.

Fig. 2B illustrates a time diagram of a quench operation. In more detail, the first line of Fig. 2B shows the power consumption of the avalanche diode arrangement 100. The second line shows incoming photons 10, the third line shows a voltage at a first node 114, the fourth line shows a output signal 150, the fifth line shows the signal 16, for enabling the second NMOS transistor 131, the sixth line shows the signal 17 for enabling the first NMOS transistor 130 and the seventh line shows the GATING signal 13.

As is shown in Fig. 2B during time ti, the GATING signal 13 is at a high level. Consequently, the signal 16 is at a low level. As is indicated by 160, each single photon detection event consumes power. During the time ti, a single photon 162 is detected. Thereafter, the voltage at the first node 114 is at a low level so that no further photon will be detected as long as signal 13 is at "1". Since time ti is an idle time for detection, there is no need to activate the detector. Accordingly, power may be saved.

The new avalanche diode arrangement 100 as described above, allows to gate the avalanche diodes 110 outside of the measurement window by activating the latch mode, i.e. the fourth mode as described above. The benefit of the latch mode, compared to completely disabling the quench circuitry is that during the latch mode the avalanche diode 110 is still able to fire once at maximum, i.e. detect a photon event. In case of no photon detection outside the window, no power is consumed. On the other hand, while in case of multiple events only a single one will cause the avalanche diode 110 to disable itself automatically. When actively disabling the avalanche diode 110 outside the measurement window, a write operation to signal 15 is necessary and all nodes 114 become discharged to GND . As a result , when leaving the gating mode , all avalanche diodes 110 need to be recharged which causes a power consumption peak on the supply . Due to the above-described operating mode , active disabling and recharging may be avoided .

Fig . 3A shows an example of a sensor 20 according to embodiments . The sensor 20 comprises the avalanche diode arrangement 100 described above .

Fig . 3B shows an example of an electronic device 30 according to embodiments . The electronic device 30 comprises the sensor 20 . For example , the electronic device 30 may be implemented as a mobile phone , an imaging device , e . g . a camera or as smart glasses . Since the described avalanche diode arrangement 100 has a reduced power consumption, the sensor 20 comprising the avalanche diode arrangement 100 may be advantageously employed in mobile devices .

Fig . 4 summarizes a method of driving an avalanche diode arrangement according to embodiments .

As is illustrated, a method of driving an avalanche diode arrangement comprising an avalanche diode comprises connecting ( S100 ) a first node of the avalanche diode arrangement to a second voltage terminal via a first transistor . A cathode of the avalanche diode is connected to the first node , an anode of the avalanche diode is connected to a first voltage terminal . The method further comprises switching-off ( Sli d ) the first transistor after a photon has been detected by the avalanche diode . This method corresponds to the fourth mode which has been explained above .

According to embodiments , the method may further comprise switching- on ( S120 ) the first transistor to re-connect the first node with the second voltage terminal .

While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein .

LIST OF REFERENCES

10 photon

13 gating signal

14 test event signal

15 SPAD activation signal

16 first activation signal

17 second activation signal

18 reset signal

20 sensor

30 electronic device

100 avalanche diode arrangement

105 core circuit

110 avalanche diode

111 anode

112 cathode

114 first node

115 first voltage terminal

116 second voltage terminal

118 second node

119 current source device

120 level shifting circuit

121 quench transistor

122 first terminal of quench transistor

123 second terminal of quench transistor

124 gate electrode of first transistor

125 first PMOS transistor

126 second PMOS transistor

127 gate electrode of second transistor

128 gating transistor

129 common bias generator

130 first NMOS transistor

131 second NMOS transistor

132 gate electrode of first transistor

133 gate electrode of second transistor

135 third NMOS transistor

136 fourth NMOS transistor 137 reset transistor

138 first gating node

139 second gating node

140 readout buffer 141 down-level shifting stage

142 pulse-shaping stage

143 capacitor

144 inverter

145 current source 150 Output signal

160 detected events

161 SPAD recharge

162 detection event

163 TDC window 164 total distance range