APPARATUS AND METHOD FOR ADAPTIVE ACTIVATION/DEACTIVATION OF AN UPLINK LAYER 2 DATAPATH AND HARDWARE THREADS BACKGROUND [0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication. [0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various procedures for uplink (UL) Layer 2 data processing. SUMMARY [0003] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a UL Layer 2 dataplane (DP) subsystem. The UL Layer 2 DP subsystem may include a set of UL packet processing blades each configured to perform UL packet processing for a plurality of concurrent component carriers (CCs). The UL Layer 2 DP subsystem may include a microcontroller (uC) that includes an uplink timing predictor (UTP) and a set of hardware threads. The UTP may be configured to receive semi-static UL timing parameters from a DP controller, a first type of dynamic UL timing parameters from a physical (PHY) layer controller, a second type of UL dynamic timing parameters from a logical channel prioritization (LCP) processing cluster associated with the set of hardware threads, and a third type of dynamic UL timing parameters from an LCP hardware cluster associated with the set of UL packet processing blades. The UTP may be configured to perform a timing analysis for a plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters. The UTP may be configured to select a minimum number of active UL packet processing blades and a minimum number of active hardware threads to meet timing requirements associated with a PHY layer for each of the plurality of concurrent CCs based on the timing analysis. [0004] According to another aspect of the present disclosure, an apparatus for wireless communication is provided. The apparatus may include a baseband chip. The baseband chip may include a UL Layer 2 DP subsystem. The UL Layer 2 DP subsystem may include a set of UL packet processing blades each configured to perform UL packet processing for a plurality of concurrent CCs. The UL Layer 2 DP subsystem may include a uC that includes a UTP and a set of hardware threads. The UTP may be configured to receive semi-static UL timing parameters from a DP controller, a first type of dynamic UL timing parameters from a PHY layer controller, a second type of UL dynamic timing parameters from a LCP processing cluster associated with the set of hardware threads, and a third type of dynamic UL timing parameters from an LCP hardware cluster associated with the set of UL packet processing blades. The UTP may be configured to perform a timing analysis for a plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters. The UTP may be configured to select a minimum number of active UL packet processing blades and a minimum number of active hardware threads to meet timing requirements associated with a PHY layer for each of the plurality of concurrent CCs based on the timing analysis. [0005] According to yet another aspect of the present disclosure, a method of wireless communication of a UL Layer 2 DP subsystem of a baseband chip is provided. The method may include performing, by a set of UL packet processing blades, UL packet processing for a plurality of concurrent CCs. The method may include receiving, by a UTP of a uC comprising a set of hardware threads, semi-static UL timing parameters from a DP controller, a first type of dynamic UL timing parameters from a PHY layer controller, a second type of UL dynamic timing parameters from an LCP processing cluster associated with the set of hardware threads, and a third type of dynamic UL timing parameters from an LCP hardware cluster associated with the set of UL packet processing blades. The method may include performing, by the UTP of the uC, a timing analysis for a plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters. The method may include selecting, by the UTP of the uC, a minimum number of active UL packet processing blades and a minimum number of active hardware threads to meet timing requirements associated with a PHY layer for each of the plurality of concurrent CCs based on the timing analysis. [0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0008] FIG.1A illustrates a first example timing diagram used to schedule a UL medium access control (MAC) protocol data unit (PDU). [0009] FIG.1B illustrates a second example timing diagram that may be used to schedule a MAC PDU. [0010] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure. [0011] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure. [0012] FIG. 4 illustrates a block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure. [0013] FIG.5 illustrates a diagram of the various inputs UTP receives to perform its timing analysis for multiple CCs, according to some embodiments of the present disclosure. [0014] FIG. 6 illustrates a diagram for a method performed by UTP to achieve a scalable low-power DP Layer 2 UL data path, according to some embodiments of the disclosure. [0015] FIGs. 7A-7D are a flowchart of an exemplary method of wireless communication, according to some embodiments of the present disclosure. [0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION [0017] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. [0018] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. [0019] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0020] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system. [0021] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. [0022] An important consideration of wireless communication relates to data rates, especially with the increased use of media streaming services. Carrier aggregation (CA) is one technique used in wireless communication to increase the data rate per user, whereby multiple frequency blocks (also referred to herein as “component carriers”) are assigned to the same UE for concurrent transmission using different parts of the frequency spectrum. Each component carrier (CC) may be associated with a different cell, e.g., base station. The maximum possible data rate per user is increased as the number of component carriers (CCs) assigned to a UE increases. CA also increases the sum data rate of a cell due to enhanced resource utilization and spectral efficiency. [0023] While communicating using CA, a UE may be connected with two or more media access control (MAC) entities, which are each connected to a base station with multiple carriers of different bandwidths, a different number of available resources, and different radio channel conditions. To schedule the transmission of uplink (UL) data packets using CA, the UE receives multiple UL grants concurrently from different base stations. Each UL grant may schedule a different logical channel packet (LCP) transmission on its respective CC. [0024] A base station may send a UL grant to the UE using the physical downlink control channel (PDCCH) of that CC. The UE may receive a UL grant at the beginning of a slot (in a downlink control indicator (DCI)), which indicates the time at which the associated MAC PDU is scheduled for transmission. The UL grant may also indicate the number of resources (e.g., byte size) that have been allocated for the MAC PDU. The scheduled time may be equivalent to a time delay of K2 slot(s) from the slot in which the UL grant is received. FIG. 1A illustrates a first example timing diagram 100 in which K2 may be one or more slots away from the received UL grant, with a transmission start symbol at the slot boundary. FIG.1B illustrates a second example timing diagram 110 in which K2 is less than one, meaning the transmission start symbol S is in the same slot in which the UL grant is received. A UL grant that schedules a MAC PDU transmission in the same slot in which the grant was received indicates that the MAC PDU may be associated with a low latency application, and hence, the UE may need to process the MAC PDU within milliseconds or microseconds. [0025] The scheduling mechanism described above may apply to each CC, and hence, the UE may process MAC PDUs for multiple CCs concurrently. One challenge that relates to the scheduling of UL MAC grant scheduling is that for the UE may have to service multiple UL MAC grants (also referred to herein as “UL grants”) from multiple cells in a multiple CA configuration in which the UE is connected to two or more MAC entities, each connected to a different base station with multiple carriers of different bandwidth, resources, and radio channel conditions. In such a scenario, the UE needs to service multiple logical channel (LC) data packets efficiently and optimally among the carriers, without any de-synchronization or loss of data. [0026] In another challenge, in order to optimize the power consumed by UE’s modem (also referred to herein as a “baseband chip”) in a multiple CA configuration, UL Layer 2 DP needs to support different application types, including high throughput high latency data transfers, as well as low latency low data rate applications. When operating in low data rate applications, the power usage should be minimized as much as possible without sacrificing quality-of-service (QoS) latency performance, or high throughput data performance. [0027] In known devices, these challenges lead to various problems, e.g., such as an inefficient usage of central processing unit (CPU) cores and DP hardware resources when processing UL Layer 2 and Layer 3 data packets, inflexible DP hardware Layer 2/Layer 3 and cipher paths, a waste of CPU cores and DP hardware during low data-rate applications, insufficient CPU and DP hardware resources during high packet-rate use cases, an inability to dynamically detect under-run or over-loaded DP data-path scenarios that violate scheduled UL transmission timing, an inability to adjust resource utilization based on UL timing requirements in dynamic mixed traffic packet use cases, high power usage for single CC low data-rate applications, just to name a few. [0028] Thus, there exists an unmet need for a baseband chip that may perform a UL timing analysis based on dynamic and semi-static input parameters, and derive the minimum resources that achieve scheduled UL transmission success. [0029] To overcome these and other challenges, the present disclosure provides a baseband chip with a scalable UL DP Layer 2 subsystem that optimizes the DP Layer 2 processing data path to achieve a dynamic resource engagement scheme that reduces power consumption. For example, the baseband chip discussed herein may include a UL Timing Predictor (UTP), which collects semi-static and dynamic input parameters from the DP controller, the physical (PHY) layer controller, a LCP processing cluster, and a UL DP hardware cluster. Using the semi-static and dynamic input parameters, the UTP may perform a UL timing analysis for multiple concurrent CCs to derive the minimum resource configuration needed for UL transmission success across each of the CCs. The minimum resource configuration may relate to the minimum number of active UL packet processing blades and a minimum number of active hardware threads (also referred to herein as LCP hardware threads”). In some instances, the derived minimum resource configuration may cause the UTP to increase the number active UL packet processing blades and/or the number of active hardware threads when additional processing resources are required. However, in some other scenarios, the derived minimum resource configuration may cause the UTP to decrease the number active UL packet processing blades and/or the number of active hardware threads in order to conserve power. Additional details related to the UTP and its UL timing analysis are provided below in connection with FIGs.2-7D. [0030] Although the following processing techniques are described in connection with Layer 2 data processing, the same or similar techniques may be applied to Layer 3 and/or Layer 4 data processing to optimize power consumption at the PHY, Layer 3, and/or Layer 4 subsystems without departing from the scope of the present disclosure. [0031] FIG.2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG.2, wireless network 200 may include a network of nodes, such as user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation. [0032] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the radio frequency (RF) in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation. [0033] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., S1 interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless. [0034] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation. [0035] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0036] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack. [0037] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible. [0038] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well. [0039] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0040] As shown in FIG.3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro- electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read- only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. [0041] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, at least two of processor 302, memory 304, and transceiver 306 are integrated into a single system- on-chip (SoC) or a single system-in-package (SiP). In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0042] Referring back to FIG. 2, in some embodiments, user equipment 202 may include a baseband chip with a scalable UL DP Layer 2 subsystem that optimizes the DP Layer 2 processing data path to achieve a dynamic resource engagement scheme that reduces power consumption. [0043] FIG. 4 illustrates a detailed block diagram an exemplary baseband chip 400, according to some embodiments of the present disclosure. [0044] As shown in FIG. 4, exemplary baseband chip 400 (referred to hereinafter as “baseband chip 400”) may include a PHY subsystem 402, a UL DP subsystem 404, a Layer 2 shared memory/external memory 420, and an application processor (AP)/host 422. As further shown in FIG. 4, UL DP subsystem 404 may include, e.g., a UL uC 408 (e.g., a uC core) that includes an LCP processing cluster 410 and a UTP 412. LCP processing cluster 410 may include a plurality of LCP threads, e.g., LCP thread 1, LCP thread 2, and LCP thread 3. Although LCP processing cluster 410 is illustrated with three LCP threads, LCP processing cluster 410 may include more or fewer LCP threads without departing from the scope of the present disclosure. [0045] Moreover, UL DP subsystem 404 may include a uC local shared memory 414, a plurality of logical channels (LCs) 416, and a UL DP hardware cluster 418. uC local shared memory 414 may be shared between UL uC 408 and the UL DP hardware cluster 418. UL DP hardware cluster 418 may include a plurality of UL DP hardware blades (also referred to herein as “a set of UL packet processing blades”). In FIG. 4, the UL data processing path includes the UL DP hardware blades, where each blade handles the data path processing for one or more UL CC(s). Each of the UL DP hardware blades may include, e.g., a transmission scheduler (TxSch), security cipher hardware and data integrity operations, packet data convergence protocol (PDCP) layer encoding hardware, window operations, radio link control (RLC) layer encoding hardware, MAC header encoding hardware, and an inline buffer (IB). Although shown with three UL DP hardware blades, UL DP hardware cluster 418 may include more or fewer UL DP hardware blades without departing from the scope of the present disclosure. Each hardware block (e.g., cipher, PDCP, RLC, MAC, etc.) may be controlled on a per packet level by the UL uC 408, through command and status queues residing in uC local shared memory 414. [0046] Each of the LCP hardware threads may be responsible for the execution of one or more of the CC(s) LCP grant processing task(s). In each LCP task corresponding to a CC’s UL grant, the thread (e.g., firmware) dequeues packet descriptors from the LC(s) 416 according to the LC priority, and constructs the Layer 2 command packet descriptors for the corresponding CC. The corresponding TxSch may cause the processing of this CC’s packet descriptors in its UL data path for transmission to PHY subsystem 402. UTP 412 may be responsible for controlling the UL processing resources for the UL DP hardware blades, as well as the LCP hardware threads. [0047] FIG.5 illustrates a diagram 500 of the various inputs UTP 412 receives to perform its timing analysis for multiple CCs, according to some embodiments of the present disclosure. As shown in FIG.5, UTP 412 takes several inputs into its algorithm, including semi-static inputs and dynamic inputs. [0048] The semi-static inputs may be received from DP controller 504 and may include, e.g., PHY Tx encoding processing time, PHY downlink control information processing time, UL cipher packet processing rate, LCP packet processing rate, the maximum throughput for each CC, according to the physical parameters (e.g., bandwidth, modulation coding scheme (MCS), the number of multiple-input multiple-output (MIMO) layers, etc.), just to name a few. [0049] Dynamic inputs may be received from PHY controller 502, LCP processing cluster 410, and the UL DP hardware cluster 418. From PHY controller 502, UTP 412 may receive a first type of dynamic UL timing parameters per CC may be received. The first type of dynamic timing parameters may include, e.g., UL grant size, grant duration (e.g., N_symbol), K2 process timing, PHY grant due time (e.g., when the symbol is due in the inline buffer of the associated UL DP hardware blade). From LCP processing cluster 410, UTP 412 may receive a second type of dynamic UL timing parameter(s). The second type of dynamic timing parameters may include, e.g., average packet size per CC, etc. From the UL DP hardware cluster 418, UTP 412 may receive a third type of dynamic timing parameter(s). The third type of dynamic UL timing parameter(s) may include, e.g., external memory (e.g., such as double data rate (DDR) memory) delay and/or NoC delay for transferring a data payload into the associated UL DP hardware blade’s inline buffer, etc. [0050] Based on these inputs, UTP 412 may perform a UL timing analysis and derive the minimum number of UL DP hardware blades and LCP threads. This may ensure that the appropriate symbols are located in the inline buffer before PHY subsystem’s 402 due time for the first symbol and every subsequent symbol, thereby ensuring UL over-the-air transmission success across multiple CCs. According to the outcome of the UL timing analysis, UTP 412 may output control signals to the UL DP hardware blades (e.g., the associated TxSch) and/or LCP threads to activate/deactivate the appropriate resources (e.g., UL DP hardware blades, LCP threads, etc.), dynamically. By dynamically activating/deactivating the optimized number of resources, baseband chip 400 may achieves the minimum power need for UL transmission, covering all use cases including, e.g., low-throughput transmissions, high-throughput transmissions, low-latency applications, high-latency applications, for multiple concurrent CCs. [0051] FIG. 6 illustrates a diagram 600 for a method performed by UTP to achieve a scalable low-power DP Layer 2 UL data path, according to some embodiments of the disclosure. Table 1 below illustrates the various time duration(s) and budget variable(s) defined by the method illustrated in the diagram 600 of FIG.6. Table 1 [0052] As shown in Fig.6, in the UL data path, the following steps are performed for each CC’s UL grant processing that schedules a UL data transmission. At 601, the PHY decodes the physical downlink control channel (PDCCH)/DCI. At 602, the PHY sends a grant indication (e.g., GrantInd) message to the Layer 2 uC. At 603, the Layer 2 uC processes the UL grant information from the grant indication message, starts the LCP task, initializes the LCP procedure, and processes any MAC control elements (CEs). At 604, the uC runs the LCP procedure and generates Layer 2 packet descriptor(s), which may be sent to the TxSch of the associated UL DP hardware blade. At 605, the TxSch dequeues the Layer 2 command packet descriptor for this CC, obtains packet data (e.g., from the external memory and/or appropriate LC), and the starts cipher process. At 606, L2 DPHW runs PDCP/RLC/MAC protocols and generates data into an Inline Buffer. At 607, which is the PHY due time, the PHY subsystem may starts dequeuing code block (CB) by CB from the inline buffer. [0053] In order to have a successful UL transmission, for each CC, the UL timing conditions (e.g., UL_TIMING_COND1 and UL_TIMING_COND2) shown below may be satisfied. UL_TIMING_COND1: T0+T1+T2+T3+Tothers < Tb (DP 1 ^st sym budget) UL_TIMING_COND2: Symbol data ready in Inline Buffer, before each Nth symbol DueTime = Tb+T_ota*(N-1) ^ [0054] In the above shown UL timing conditions, Tothers may be the time slice allocated/interleaved for other CC’s LCP and cipher processing, if multiple concurrent CCs are scheduled within a single LCP hardware thread and/or Layer 2 cipher resource. Tothers may be set to 0 if only one CC per LCP hardware thread and/or Layer 2 cipher resource is scheduled. This analysis may be performed by the UTP dynamically to evaluate the optimized resources for successful UL transmission. [0055] FIGs. 7A-7D are a flowchart of an exemplary method 700 of wireless communication, according to some embodiments of the present disclosure. Method 700 may be performed by an apparatus for wireless communication, e.g., such as a user equipment, a baseband chip, a UL DP subsystem, a UL Layer 2 uC, or a UTP, just to name a few. Method 700 may include steps 702-740 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIGs.7A-7D. [0056] Referring to FIG. 7A, at 702, the apparatus may be in idle mode. At 704, the apparatus may initialize DP control configuration setup parameters per CC, system configurations with 1 LCP hardware thread, and one UL Layer 2 DP hardware blade. At 706, the apparatus may enter connected mode. At 708, the apparatus may receive, for one or more CCs, a PHY grant indication, and may calculate Tb = DP Budget to 1 ^st Symbol, based on PHY grant indication, where Tb = Tproc2 – Tp0 – Tp1. At 710, the apparatus may apply filtering of average packet size (S_pkt), for all LCs served by this PHY grant/CC. At 712, the apparatus may apply filtering of DDR_NoC_Delay (T2) from the UL DP hardware cluster. At 714, the apparatus may calculate the number of packets per symbol Npkt_sym = (GrantSz/N_sym) / S_pkt. One symbol refers to the PHY layer transmission symbol, depending on the frequency and coding rate, etc., the symbol time, and size variation. Here, the system may calculate the grant size that each symbol can transmit based on the total grant size allocated by the base station in each transport block (TB). The number of symbols in each TB may be a pre-determined value (e.g., 14 symbols), which is denoted above as N_sym. Then the system may derive the approximate number of packets that can be transmitted in each symbol, e.g., namely the number of grant bytes in each symbol, divided by the average packet size. [0057] Referring to FIG. 7B, at 716, the apparatus may derive cipher processing time per symbol: T_cipher_sym (T3) = Npkt_sym * t_cipher_pp, where t_cipher_pp = cipher time per pkt based on pktsz, and per pkt overhead. At 718, the apparatus may derive LCP processing time per symbol: T_LCP_sym (T1) = Npkt_sym * t_lcp_pp, where t_lcp_pp = LCP process time per pkt. At 720, the apparatus may determine whether a first UL timing condition (UL_TIMING_COND1) is met. The first UL timing condition may be associated with a DP first symbol budget. For example, determining whether the first UL timing condition may include calculating T0+T1+T2+T3+Tothers < Tb. In response to the first UL timing condition being met, the operations may move to 722. On the other hand, in response to the first UL timing condition not being met, the operations may move to 730 in FIG. 7D. At 722, the apparatus may determine whether a second timing condition is met (UL_TIMING_COND2). For example, determining whether the second UL timing condition is met may include determining whether symbol data is ready in an inline buffer before each Nth symbol due time. This may be calculated as, e.g., DueTime = Tb+T_ota*(N-1). In response to the second UL timing condition being met, the operations may move to 726 in FIG.7C. Otherwise, in response to the second UL timing condition not being met, the operations may move to 730 in FIG.7D. [0058] Referring to FIG.7C, at 724, the apparatus may determine a low power (LP) count. At 726, the apparatus may determine whether the LP count is greater than an LP threshold. Here, a counter and LP threshold number may be used to guide against a temperature spike. The system may count the number of times an LP condition is triggered until the LP threshold number is reached reducing the resources. In response to the LP count being greater than the LP threshold, the operation may move to 728. Otherwise, in response to the LP count being less than or equal to the LP threshold, the operations may return to 708 in FIG. 7A. Still referring to FIG. 7C, at 728, the apparatus may turn off one UL DP hardware blade and reduce the number of active LCP hardware threads by one. Then, the operations may return to 708 in FIG.7A. [0059] Referring to FIG. 7D, at 730, the apparatus may determine whether T_cipher_sym > T_LCP_sym + Thresh1. In response to T_cipher_sym being greater than T_LCP_sym + Thresh1, the operations may move to 732. Otherwise, when T_cipher_sym being less than T_LCP_sym + Thresh1, the operations may move to 734. At 732, the apparatus may turn on one additional UL DP hardware blade. Then, the operations may return to 708 in FIG. 7A. At 734, the apparatus may determine whether T_LCP_sym > T_cipher_sym + Thresh2. In response to T_LCP_sym being greater than T_cipher_sym + Thresh2, the operations may move to 736. On the other hand, when T_LCP_sym is less than or equal to T_cipher_sym + Thresh2, the operations may move to 738. At 736, the apparatus may turn on (e.g., active) one additional LCP hardware thread. Then, the operations may return to 708 in FIG.7A. Still referring to FIG.7D, at 738, the apparatus may turn on (e.g., activate) one additional LCP hardware thread and turn on one additional UL DP hardware blade. [0060] By providing the apparatus(es) and method(s) described above, power consumption by the UL DP subsystem may be reduced, while optimally utilizing the CPU core resources and hardware resources for various traffic pattern use cases. In addition, the processor resources, memories, and HW resources during low data rate traffic, single CC cases may be reduced. These resources and uC processor cores, as well as the associated local memories, Layer 2 hardware (e.g., cipher, PDCP, RLC, MAC, etc.) and NoC interconnect resources, e.g., such as bus transactions, external DDR memory access, etc., may be optimized to minimum levels during low data rate applications. Furthermore, the present techniques may provide a flexible and scalable DP Layer 2 architecture, which can be controlled dynamically according to traffic throughput and latency, and number of multiple CCs Still further, optimized resource usage based on UL timing requirements in dynamic, mixed traffic packet multiple CC use cases that ensure UL transmission success may be achieved using the above described techniques. The present technique(s), apparatus(es), and method(s) may provide an expandable, programmable and reusable architecture for 6G, 7G, etc., as well as Wi-Fi 6/7 and beyond, satellite technologies, automotive technologies, among others. The same or similar technique(s), apparatus(es), and/or method(s) may also be applied to other subsystems such as the PHY subsystem and/or the DP Layer 3 subsystem. [0061] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0062] According to one aspect of the present disclosure, a baseband chip is provided. The baseband chip may include a UL Layer 2 DP subsystem. The UL Layer 2 DP subsystem may include a set of UL packet processing blades each configured to perform UL packet processing for a plurality of concurrent CCs. The UL Layer 2 DP subsystem may include a uC that includes a UTP and a set of hardware threads. The UTP may be configured to receive semi-static UL timing parameters from a DP controller, a first type of dynamic UL timing parameters from a PHY layer controller, a second type of UL dynamic timing parameters from a LCP processing cluster associated with the set of hardware threads, and a third type of dynamic UL timing parameters from an LCP hardware cluster associated with the set of UL packet processing blades. The UTP may be configured to perform a timing analysis for a plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters. The UTP may be configured to select a minimum number of active UL packet processing blades and a minimum number of active hardware threads to meet timing requirements associated with a PHY layer for each of the plurality of concurrent CCs based on the timing analysis. [0063] In some embodiments, the UTP may be further configured to output a first set of control signals to activate or deactivate one or more of the set of hardware threads to achieve the minimum number of active hardware threads to meet the timing requirements associated with the PHY layer. In some embodiments, the UTP may be further configured to output a second set of control signals to activate or deactivate one or more of the set of UL packet processing blades to achieve the minimum number of active UL packet processing blades to meet the timing requirements of the PHY layer. [0064] In some embodiments, the minimum number of active hardware threads may be configured to output UL packet processing commands to the minimum number of active UL packet processing blades. [0065] In some embodiments, the semi-static UL timing parameters may include, for each of the plurality of CCs, one or more of a PHY transmission encoding processing time, a PHY DCI processing time, a cipher packet rate, an LCP packet rate, or a maximum throughput. In some embodiments, the first type of UL dynamic timing parameters may include, for each of the plurality of CCs, one or more of a UL grant size, a UL grant duration per symbol, a K2 packet processing time, and an inline buffer PHY due time. In some embodiments, the second type of UL dynamic timing parameters may include, for each of the plurality of CCs, average packet size. In some embodiments, the third type of UL dynamic timing parameters include an external memory or NoC delay. [0066] In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the first type of dynamic UL timing parameters, a DP timing budget for a first symbol for one or more CCs, the DP timing budget being associated with a time the first symbol is due in an inline buffer of the UL Layer 2 DP subsystem, and the first type of dynamic UL timing parameters being associated with a UL grant. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the second type of UL dynamic timing parameters, an average UL packet size for each LC served by the UL grant. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the third type of dynamic UL timing parameters, a delay associated with an external memory. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the average UL packet size for each LC served by the UL grant and the delay associated with the external memory, a number of symbols per UL packet. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the semi-static UL timing parameters, a cipher processing time per symbol based on packet size and packet overhead. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the semi-static UL timing parameters, an LCP processing time per symbol based at least in part on an LCP processing time per UL packet. [0067] In some embodiments, the UTP may be further configured to, in response to determining that a first UL timing condition is met based on one or more of the DP timing budget for a first symbol for one or more CCs, the average UL packet size for each LC served by the UL grant, the delay associated with a memory external to the UL Layer 2 DP subsystem, the number of symbols per UL packet, the cipher processing time per symbol based at least in part on packet size and packet overhead, or the LCP processing time per symbol based at least in part on the LCP processing time per UL packet, determine whether a second UL timing condition is met. In some embodiments, the UTP may be further configured to, in response to determining that the second UL timing condition is met based on whether at least one symbol is ready in the inline buffer of the UL Layer 2 DP subsystem prior to a PHY layer due time, reduce a number of the active UL packet processing blades. [0068] In some embodiments, the UTP may be further configured to, in response to determining that the first UL timing condition is not met, determine whether the cipher processing time for one symbol is greater than a delay in LCP command generation plus a first threshold. In some embodiments, the UTP may be further configured to, in response to determining that the cipher processing time for one symbol is greater than the delay in LCP command generation plus the first threshold, increase a number of active UL packet processing blades. In some embodiments, the UTP may be further configured to, in response to determining that the cipher processing time for one symbol is not greater than the delay in LCP command generation plus the first threshold, determine whether the delay in LCP command generation is greater than the cipher processing time for one symbol plus a second threshold. In some embodiments, the UTP may be further configured to, in response to determining that the LCP command generation is greater than the cipher processing time for one symbol plus a second threshold, increase a number of active hardware threads. In some embodiments, the UTP may be further configured to, in response to determining that the LCP command generation is not greater than the cipher processing time for one symbol plus a second threshold, increase the number of active UL packet processing blades and the number of active hardware threads. [0069] According to another aspect of the present disclosure, an apparatus for wireless communication is provided. The apparatus may include a baseband chip. The baseband chip may include a UL Layer 2 DP subsystem. The UL Layer 2 DP subsystem may include a set of UL packet processing blades each configured to perform UL packet processing for a plurality of concurrent CCs. The UL Layer 2 DP subsystem may include a uC that includes a UTP and a set of hardware threads. The UTP may be configured to receive semi-static UL timing parameters from a DP controller, a first type of dynamic UL timing parameters from a PHY layer controller, a second type of UL dynamic timing parameters from a LCP processing cluster associated with the set of hardware threads, and a third type of dynamic UL timing parameters from an LCP hardware cluster associated with the set of UL packet processing blades. The UTP may be configured to perform a timing analysis for a plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters. The UTP may be configured to select a minimum number of active UL packet processing blades and a minimum number of active hardware threads to meet timing requirements associated with a PHY layer for each of the plurality of concurrent CCs based on the timing analysis. [0070] In some embodiments, the UTP may be further configured to output a first set of control signals to activate or deactivate one or more of the set of hardware threads to achieve the minimum number of active hardware threads to meet the timing requirements associated with the PHY layer. In some embodiments, the UTP may be further configured to output a second set of control signals to activate or deactivate one or more of the set of UL packet processing blades to achieve the minimum number of active UL packet processing blades to meet the timing requirements of the PHY layer. [0071] In some embodiments, the minimum number of active hardware threads may be configured to output UL packet processing commands to the minimum number of active UL packet processing blades. [0072] In some embodiments, the semi-static UL timing parameters may include, for each of the plurality of CCs, one or more of a PHY transmission encoding processing time, a PHY DCI processing time, a cipher packet rate, an LCP packet rate, or a maximum throughput. In some embodiments, the first type of UL dynamic timing parameters may include, for each of the plurality of CCs, one or more of a UL grant size, a UL grant duration per symbol, a K2 packet processing time, and an inline buffer PHY due time. In some embodiments, the second type of UL dynamic timing parameters may include, for each of the plurality of CCs, average packet size. In some embodiments, the third type of UL dynamic timing parameters include an external memory or NoC delay. [0073] In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the first type of dynamic UL timing parameters, a DP timing budget for a first symbol for one or more CCs, the DP timing budget being associated with a time the first symbol is due in an inline buffer of the UL Layer 2 DP subsystem, and the first type of dynamic UL timing parameters being associated with a UL grant. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the second type of UL dynamic timing parameters, an average UL packet size for each LC served by the UL grant. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the third type of dynamic UL timing parameters, a delay associated with an external memory. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the average UL packet size for each LC served by the UL grant and the delay associated with the external memory, a number of symbols per UL packet. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the semi-static UL timing parameters, a cipher processing time per symbol based on packet size and packet overhead. In some embodiments, to perform the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters, the UTP may be further configured to determine, based on the semi-static UL timing parameters, an LCP processing time per symbol based at least in part on an LCP processing time per UL packet. [0074] In some embodiments, the UTP may be further configured to, in response to determining that a first UL timing condition is met based on one or more of the DP timing budget for a first symbol for one or more CCs, the average UL packet size for each LC served by the UL grant, the delay associated with a memory external to the UL Layer 2 DP subsystem, the number of symbols per UL packet, the cipher processing time per symbol based at least in part on packet size and packet overhead, or the LCP processing time per symbol based at least in part on the LCP processing time per UL packet, determine whether a second UL timing condition is met. In some embodiments, the UTP may be further configured to, in response to determining that the second UL timing condition is met based on whether at least one symbol is ready in the inline buffer of the UL Layer 2 DP subsystem prior to a PHY layer due time, reduce a number of the active UL packet processing blades. [0075] In some embodiments, the UTP may be further configured to, in response to determining that the first UL timing condition is not met, determine whether the cipher processing time for one symbol is greater than a delay in LCP command generation plus a first threshold. In some embodiments, the UTP may be further configured to, in response to determining that the cipher processing time for one symbol is greater than the delay in LCP command generation plus the first threshold, increase a number of active UL packet processing blades. In some embodiments, the UTP may be further configured to, in response to determining that the cipher processing time for one symbol is not greater than the delay in LCP command generation plus the first threshold, determine whether the delay in LCP command generation is greater than the cipher processing time for one symbol plus a second threshold. In some embodiments, the UTP may be further configured to, in response to determining that the LCP command generation is greater than the cipher processing time for one symbol plus a second threshold, increase a number of active hardware threads. In some embodiments, the UTP may be further configured to, in response to determining that the LCP command generation is not greater than the cipher processing time for one symbol plus a second threshold, increase the number of active UL packet processing blades and the number of active hardware threads. [0076] According to yet another aspect of the present disclosure, a method of wireless communication of a UL Layer 2 DP subsystem of a baseband chip is provided. The method may include performing, by a set of UL packet processing blades, UL packet processing for a plurality of concurrent CCs. The method may include receiving, by a UTP of a uC comprising a set of hardware threads, semi-static UL timing parameters from a DP controller, a first type of dynamic UL timing parameters from a PHY layer controller, a second type of UL dynamic timing parameters from an LCP processing cluster associated with the set of hardware threads, and a third type of dynamic UL timing parameters from an LCP hardware cluster associated with the set of UL packet processing blades. The method may include performing, by the UTP of the uC, a timing analysis for a plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters. The method may include selecting, by the UTP of the uC, a minimum number of active UL packet processing blades and a minimum number of active hardware threads to meet timing requirements associated with a PHY layer for each of the plurality of concurrent CCs based on the timing analysis. [0077] In some embodiments, the method may include outputting, by the UTP of the uC, a first set of control signals to activate or deactivate one or more of the set of hardware threads to achieve the minimum number of active hardware threads to meet the timing requirements associated with the PHY layer. In some embodiments, the method may include outputting, by the UTP of the uC, a second set of control signals to activate or deactivate one or more of the set of UL packet processing blades to achieve the minimum number of active UL packet processing blades to meet the timing requirements of the PHY layer. [0078] In some embodiments, the method may include outputting, by the minimum number of active hardware threads, UL packet processing commands to the minimum number of active UL packet processing blades. [0079] In some embodiments, the semi-static UL timing parameters may include, for each of the plurality of CCs, one or more of a PHY transmission encoding processing time, a PHY DCI processing time, a cipher packet rate, an LCP packet rate, or a maximum throughput. In some embodiments, the first type of UL dynamic timing parameters may include, for each of the plurality of CCs, one or more of a UL grant size, a UL grant duration per symbol, a K2 packet processing time, and an inline buffer PHY due time. In some embodiments, the second type of UL dynamic timing parameters may include, for each of the plurality of CCs, average packet size. In some embodiments, the third type of UL dynamic timing parameters include an external memory or NoC delay. [0080] In some embodiments, the performing, by the UTP of the uC, the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters may include determining, based on the first type of dynamic UL timing parameters, a DP timing budget for a first symbol for one or more CCs, the DP timing budget being associated with a time the first symbol is due in an inline buffer of the UL Layer 2 DP subsystem, and the first type of dynamic UL timing parameters being associated with a UL grant. In some embodiments, the performing, by the UTP of the uC, the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters may include determining, based on the second type of UL dynamic timing parameters, an average UL packet size for each LC served by the UL grant. In some embodiments, the performing, by the UTP of the uC, the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters may include determining, based on the third type of dynamic UL timing parameters, a delay associated with an external memory. In some embodiments, the performing, by the UTP of the uC, the timing analysis for the plurality of concurrent CCs based on the semi- static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters may include determining, based on the average UL packet size for each LC served by the UL grant and the delay associated with the external memory, a number of symbols per UL packet. In some embodiments, the performing, by the UTP of the uC, the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters may include determining, based on the semi-static UL timing parameters, a cipher processing time per symbol based on packet size and packet overhead. In some embodiments, the performing, by the UTP of the uC, the timing analysis for the plurality of concurrent CCs based on the semi-static UL timing parameters, the first type of dynamic UL timing parameters, the second type of UL dynamic timing parameters, and the third type of UL dynamic timing parameters may include determining, based on the semi-static UL timing parameters, an LCP processing time per symbol based at least in part on an LCP processing time per UL packet. [0081] In some embodiments, in response to determining that a first UL timing condition is met based on one or more of the DP timing budget for a first symbol for one or more CCs, the average UL packet size for each LC served by the UL grant, the delay associated with a memory external to the UL Layer 2 DP subsystem, the number of symbols per UL packet, the cipher processing time per symbol based at least in part on packet size and packet overhead, or the LCP processing time per symbol based at least in part on the LCP processing time per UL packet, the method may include determining, by the UTP of the uC, whether a second UL timing condition is met. In some embodiments, in response to determining that the second UL timing condition is met based on whether at least one symbol is ready in the inline buffer of the UL Layer 2 DP subsystem prior to a PHY layer due time, the method may include reducing, by the UTP of the uC, a number of the active UL packet processing blades. In some embodiments, in response to determining that the first UL timing condition is not met, the method may include determining, by the UTP of the uC, whether the cipher processing time for one symbol is greater than a delay in LCP command generation plus a first threshold. In some embodiments, in response to determining that the cipher processing time for one symbol is greater than the delay in LCP command generation plus the first threshold, the method may include increasing, by the UTP of the uC, a number of active UL packet processing blades. In some embodiments, in response to determining that the cipher processing time for one symbol is not greater than the delay in LCP command generation plus the first threshold, the method may include determining, by the UTP of the uC, whether the delay in LCP command generation is greater than the cipher processing time for one symbol plus a second threshold. In some embodiments, in response to determining that the LCP command generation is greater than the cipher processing time for one symbol plus a second threshold, the method may include increasing, by the UTP of the uC, a number of active hardware threads. In some embodiments, in response to determining that the LCP command generation is not greater than the cipher processing time for one symbol plus a second threshold, the method may include increasing, by the UTP of the uC, the number of active UL packet processing blades and the number of active hardware threads. [0082] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. [0083] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0084] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. [0085] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. [0086] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.