This invention relates to analogue conversion of pulse width modulated (PWM) signals.

Pulse width modulation of a signal involves the modulation of the duty cycle (D) of the signal in order to carry data in a "digital form", where the duty cycle is the fraction of time that a system is in an "active" state. For example, in an ideal pulse train (having rectangular pulses), the duty cycle is the pulse duration divided by the pulse period, and represents the data value carried by the signal. In some situations it may be preferable to carry data using a PWM signal in this way.

However, in other situations it may be preferable to express the data in an analogue voltage signal by an analogue voltage level of the signal. Converters are known which convert PWM signals into analogue voltage signals. The converters may include an amplifier and other components. The accuracy of a converted signal may be adversely affected by the offset of the amplifier and any components mismatch in the converter.

It is an aim of the present invention to provide a method and apparatus for converting a PWM signal to an analogue voltage signal that address the problem of amplifier offset and/or component mismatch.

In a first aspect there is provided a method of converting an input signal into a voltage output signal, the input signal being a periodic pulse width modulated signal, the input signal being in an active state for a first portion of each of successive time periods and being in an inactive state for a second portion of each time period, the method comprising: during the first portion of a first time period of the input signal, supplying a high voltage to a first input of an integrator circuit and supplying a low voltage to a second input of the integrator circuit, the integrator circuit comprising a first output coupled to the first input via a first capacitor, and comprising a second output coupled to the second input via a second capacitor, whereby the first and second capacitors are charged to have respectively opposite charge states; during the second portion of the first time period of the input signal, supplying a low voltage to the first input of the integrator circuit and supplying a high voltage to the second input of the integrator circuit to thereby charge the first and second capacitors with respectively reversed current; holding, at a hold capacitor, the voltage difference between the voltage at the first output of the integrator circuit and the voltage at the second output of the integrator circuit at the end of the first time period of the input signal; discharging the first and second capacitors during a second time period of the input signal; during the first portion of a third time period of the input signal, supplying a low voltage to the first input of the integrator circuit and supplying a high voltage to the second input of the integrator circuit; during the second portion of the third time period of the input signal, supplying a high voltage to the first input of the integrator circuit and supplying a low voltage to the second input of the integrator circuit; holding, at the hold capacitor, the voltage difference between the second output of the integrator circuit and the first output of the integrator circuit at the end of the third time period of the input signal; and using the voltage held at the hold capacitor to provide the voltage output signal.

In a second aspect there is provided a converter for converting an input signal into a voltage output signal, the input signal being a periodic pulse width modulated signal, the input signal being in an active state for a first portion of each of successive time periods and being in an inactive state for a second portion of each time period, the converter comprising: an integrator circuit comprising a first output coupled to a first input via a first capacitor, and comprising a second output coupled to a second input via a second capacitor; supply means for supplying, during the first portion of a first time period of the input signal, a high voltage to the first input of the integrator circuit and supplying a low voltage to the second input of the integrator circuit, to charge the first and second capacitors to have respectively opposite charge states, the supply means being configured to, during the second portion of the first time period of the input signal, supply a low voltage to the first input of the integrator circuit and supply a high voltage to the second input of the integrator circuit to thereby charge the first and second capacitors with respectively reversed current; a hold capacitor configured to hold the voltage difference between the voltage at the first output of the integrator circuit and the voltage at the second output of the integrator circuit at the end of the first time period of the input signal; and means for discharging the first and second capacitors during a second time period of the input signal; wherein the supply means are configured to, during the first portion of a third time period of the input signal, supply a low voltage to the first input of the integrator circuit and supply a high voltage to the second input of the integrator circuit, and wherein the supply means are further configured to, during the second portion of the third time period of the input signal, supply a high voltage to the first input of the integrator circuit and supply a low voltage to the second input of the integrator circuit, wherein the hold capacitor is configured to hold the voltage difference between the second output of the integrator circuit and the first output of the integrator circuit at the end of the third time period of the input signal, and wherein the voltage held at the hold capacitor is used to provide the voltage output signal.

For a better understanding of the present invention and to show how the same may be put into effect, reference will now be made, by way of example, to the following drawings in which:

Figure 1 is a schematic circuit diagram representing the converter circuit of the present invention according to a preferred embodiment;

Figure 2 is a signal diagram showing the operation of the converter circuit according to a preferred embodiment;

Figure 3 is a schematic circuit diagram representing the converter circuit of the present invention according to a second embodiment;

Figure 4 shows simulation graphs for the converter circuit of an embodiment in which D=O.5, V _Off =5mV, ΔR=0.1 R and ΔC=0.1 C; Figure 5 shows simulation graphs for the converter circuit of an embodiment in which D=0.6, V _Off =5mV, ΔR=0.1 R and ΔC=0.1C; and

Figure 6 shows simulation graphs for the converter circuit of an embodiment in which D=0.4, V _Off =5mV, ΔR=0.1 R and ΔC=0.1 C. Reference is first made to Figure 1 , which illustrates the converter circuit 100 of the present invention according to a preferred embodiment. The converter circuit 100 comprises an xOR gate 102, an inverter 104, a first resistor 106, a second resistor 108, an OP AMP 110 with differential inputs and differential outputs (OP, OM), a first capacitor 112, a second capacitor 114, a third capacitor 116, a fourth capacitor 118, a first switch 120, a second switch 122, a third switch 124, a fourth switch 126, a fifth switch 128, a sixth switch 130, a seventh switch 132, an eighth switch 134, a ninth switch 136, a tenth switch 138, an eleventh switch 140, a twelfth switch 142, a sampling capacitor 144, a thirteenth switch 146, a fourteenth switch 148, an output buffer 150 and a hold capacitor 152.

The PWM signal is used as a first clock signal Q-i. The PWM signal is also input into divider circuitry (not shown) to generate a second clock signal Q ₂ having a period that is twice the period of the first clock signal Q-i. Further divider circuitry (also not shown) is used to generate a third clock signal Q3 which has a period that is three times the period of the first clock signal Qi. Non-overlapping switching clock circuitry (not shown ) is used to generate an inverted first clock signal nQi from the first clock signal Q-i, to generate an inverted second clock signal nQ ₂ from the second clock signal Q ₂ , and to generate an inverted third clock signal nQ ₃ from the third clock signal Q ₃ .

The PWM input signal is coupled to a first input of the xOR gate 102. The third clock signal Q ₃ is coupled to a second input of the xOR gate 102. The output of the xOR gate 102 is coupled to the first resistor 106. The output of the xOR gate 102 is also coupled to an input of the inverter 104. An output of the inverter 104 is coupled to the second resistor 108. A first input of the OP AMP 110 is coupled to the first resistor 106 and a second input of the OP AMP 110 is coupled to the second resistor 108.

There is a first feedback path between a first output and the first input of the OP AMP 110 as described herein. The first output of the OP AMP 110 is coupled to the first capacitor 112 and to the third capacitor 116. The first capacitor 112 is coupled to the first input of the OP AMP 110 via the first switch 120. The third capacitor 116 is coupled to the first input of the OP AMP 110 via the fifth switch 128. The two sides of the first capacitor 112 are connected to each other via the sixth switch 130. The two sides of the third capacitor are connected to each other via the second switch 122. The first and second switches 120,122 are operated in accordance with the inverted second clock signal nQ ₂ . The fifth and sixth switches 128,130 are operated in accordance with the second clock signal Q2.

Similarly, there is a second feedback path between a second output and the second input of the OP AMP 110 as described herein. The second output of the OP AMP 110 is coupled to the second capacitor 114 and to the fourth capacitor 118. The second capacitor 114 is coupled to the second input of the OP AMP 110 via the third switch 124. The fourth capacitor 118 is coupled to the second input of the OP AMP 110 via the seventh switch 132. The two sides of the second capacitor 114 are connected to each other via the eighth switch 134. The two sides of the fourth capacitor are connected to each other via the fourth switch 126. The third and fourth switches 124,126 are operated in accordance with the inverted second clock signal nQ ₂ . The seventh and eighth switches 132,134 are operated in accordance with the second clock signal Q ₂ .

The first output of the OP AMP 110 is coupled to a first side of the sampling capacitor 144 via the ninth switch 136 and is coupled to a second side of the sampling capacitor 144 via the eleventh switch 140. The second output of the OP AMP 110 is coupled to the first side of the sampling capacitor 144 via the twelfth switch 142 and is coupled to the second side of the sampling capacitor 144 via the tenth switch 138. The inverted first clock signal nQi and the third clock signal Q ₃ are subjected to an AND operation to generate a fourth clock signal (nQi.Qa). The inverted first clock signal nQ-j and the inverted third clock signal Q ₃ are subjected to an AND operation to generate a fifth clock signal (nQi.nQ ₃ ). The ninth and tenth switches 136, 138 are operated in accordance with the fifth clock signal (nQi.nQ ₃ ). The eleventh and twelfth switches 140, 142 are operated in accordance with the fourth clock signal (nQi.Q ₃ ). The first side of the sampling capacitor 144 is coupled to a reference voltage supply V _rθf via the fourteenth switch 148. The second side of the sampling capacitor is coupled to a first input of the buffer 150 via the thirteenth switch 146. The thirteenth and fourteenth switches 146, 148 are operated in accordance with the first clock signal Q-|. The output of the buffer 150 is coupled to a second input of the buffer 150. The output of the buffer 150 is coupled to a first side of the hold capacitor 152. A second side of the hold capacitor 152 is connected to ground.

The operation of the converter circuit 100 is now described with reference to figures 1 and 2. Figure 2 is a signal diagram showing the operation of the converter circuit 100 of figure 1.

During the first time period of the PWM signal T-i, the PWM signal is high for a time interval ti and low for a time interval t ₂ as shown in figure 2. During time interval t-i, the first clock signal (Qi) is high, whilst the second and third clock signals (Q ₂ and Q ₃ ) are low. The result of this is that the output of the xOR gate 102 is high, such that a high voltage is supplied to the first resistor 106 and a low voltage is supplied to the second resistor 108. For example, the voltage supplied to the first resistor 106 has a value VIN relative to the voltage supplied to the second resistor 108.

During time interval ti the second clock signal Q ₂ is low. This results in the first, second, third and fourth switches (120, 122, 124, 126) being closed and the fifth, sixth, seventh and eighth switches (128, 130, 132, 134) being open. Therefore, during time interval ti the first capacitor 112 is connected between the first output (OP) and the first input of the OP AMP 110, and the second capacitor 114 is connected between the second output (OM) and the second input of the OP AMP 110. The third capacitor 116 and the fourth capacitor 118 are short-circuited by closing the second and fourth switches 122, 126 such that the third and fourth capacitors 116, 118 are discharged during time interval t-i. The voltage V _O p at the first output of the OP AMP 110 can be calculated as follows:

where t is time, h is the current flowing into the first capacitor 112 and through the first resistor 106, and Vc is the common voltage at the input of the OP AMP 110 (Vc=V _n =Vp).

Similarly, the voltage V _O M at the second output of the OP AMP 110 can be calculated as follows:

where I ₂ is the current flowing into the second capacitor 114 and through the second resistor 108. The resistance Ri of the first resistor 106 is chosen to be equal to the resistance R ₂ of the second resistor 108. However, there may be some slight discrepancy in the resistance of the two resistors caused by component mismatching.

Figure 2 shows that during time period ti V _O p is decreased at a rate of

During time interval ti the first clock signal Qi is high. Therefore, the fourth clock signal (nQi.Qs) and the fifth clock signal (nQi.nQ ₃ ) are low. This results in the ninth, tenth, eleventh and twelfth switches 136, 138, 140, 142 being open. The sampling capacitor 144 is therefore disconnected from the OP AMP 110 and the differential output voltage Vo across the sampling capacitor is low, as shown in Figure 2. During time interval t ₂ , the first, second and third clock signals (Q-i, Q ₂ and Q ₃ ) are low. The result of this is that the output of the xOR gate 102 is low, such that a low voltage is supplied to the first resistor 106 and a high voltage is supplied to the second resistor 108. For example, the voltage supplied to the second resistor 108 has a value VIN relative to the voltage supplied to the first resistor 106.

Similarly to during time interval t-i, during time interval t ₂ the second clock signal Q ₂ is low. This means that the first to eighth switches (120 to 134) and the first to fourth capacitors (112 to 118) are arranged as described above in relation to time interval t-i.

A similar calculation to that described above in relation to time interval t-i, leads to the result that during the time interval t ₂ the voltage V _O p is increased

at a rate of as shown in figure 2.

During time interval t ₂ the first clock signal Qi and the third clock signal Q ₃ are low. Therefore the fourth clock signal (nQ-i.Qs) is low and the fifth clock signal (nQi.nQ ₃ ) is high. This results in the ninth and tenth switches (136, 138) being closed and the eleventh and twelfth switches (140, 142) being open. The first output (OP) of the OP AMP 110 is connected to the first side of the sampling capacitor 144 via the ninth switch 136 and the second output (OM) of the OP AMP 110 is connected to the second side of the sampling capacitor 144 via the tenth switch 138. The differential output voltage V ₀ across the sampling capacitor 144 is given by the voltage difference between the two outputs of the OP AMP 110 (i.e. V ₀ = V _0M -V _0P ). The difference between

V _0M and V _0P is ramped up during ti such that at the start of time interval t ₂ the differential output voltage V ₀ has a high value, as shown in figure 2. However, during time interval t ₂ the differential output voltage V ₀ is ramped down as shown in figure 2. Due to the difference in the duration of time intervals ti and t ₂ and due to possible differences in the values of Ri and R ₂ and in the values of Ci and C ₂ , the differential output voltage V ₀ may be non-zero at the end of time interval t ₂ (i.e. at the end of the first time period Ti of the PWM signal). This can be seen, as an example, in figure 2.

The output voltage at the end of the first period of the PWM signal Ti is given by:

V ' OX - ~ V ' OM — V ' OP

where V _OF F is an offset voltage of the OP AMP 110 and D is the duty cycle of the PWM signal, such that the time interval ti has a duration DT and the time interval t ₂ has a duration (1-D)T.

During the second time period of the PWM signal T ₂ , the PWM signal is high for a time interval t ₃ and low for a time interval t ₄ as shown in figure 2. During time interval t. ₃ , the first and second clock signals (Qi and Q ₂ ) are high whilst the third clock signal (Q ₃ ) is low.

Since the first clock signal Qi is high during the time interval t ₃ , the ninth to twelfth switches (136 to 142) are open and the thirteenth and fourteenth switches (146, 148) are closed. This means that the sampling capacitor 144 is disconnected from the outputs of the OP AMP 110. Furthermore, the first side of the sampling capacitor 144 is connected to a reference voltage V _ref via the fourteenth switch 148 and the second side of the sampling capacitor 144 is connected to the buffer 150 via the thirteenth switch 146. In this way, the voltage held at the sampling capacitor 144 at the end of time interval t ₂ is passed to the hold capacitor 152 via the buffer 150. The voltage passed to the hold capacitor 152 is held at the hold capacitor for the duration of the second period of the PWM signal T ₂ as represented by V _H in Figure 2. During time interval t ₃ the output of the xOR gate 102 is high, such that a high voltage is supplied to the first resistor 106 and a low voltage is supplied to the second resistor 108. For example, the voltage supplied to the first resistor 106 has a value V| _N relative to the voltage supplied to the second resistor 108.

During time interval t ₃ the second clock signal Q ₂ is high such that the first, second, third and fourth switches (120, 122, 124, 126) are open, and the fifth, sixth, seventh and eighth switches (128, 130, 132, 134) are closed. Therefore, during time period t ₃ the third capacitor 116 is connected between the first output (OP) and the first input of the OP AMP 110, and the fourth capacitor 118 is connected between the second output (OM) and the second input of the OP AMP 110. The first capacitor 112 and the second capacitor 114 are short-circuited by closing the sixth and eighth switches 130, 134 such that the first and second capacitors 112, 114 are discharged during time interval tβ.

A similar calculation to that described above in relation to time interval t-i, leads to the result that during the time interval t ₃ the voltage at the first output of the OP AMP, V _O p is given by: V _{op + const t} and the voltage at the second output of the OP AMP, V _0M is given by: .

Figure 2 shows that during time interval t ₃ V _O p is decreased at a rate of

( —v - -v Λ . During time interval t ₃ V _0M is increased at a rate of ( ' v ^c Λ '

During time interval U, the first and third clock signals (Qi and Q ₃ ) are low whilst the second clock signal (Q ₂ ) is high. The result of this is that the output of the xOR gate 102 is low, such that a low voltage is supplied to the first resistor 106 and a high voltage is supplied to the second resistor 108. For example, the voltage supplied to the second resistor 108 has a value VIN relative to the voltage supplied to the first resistor 106.

Similarly to during time interval t ₃ , during time interval t ₄ the second clock signal Q ₂ is high. This means that the first to eighth switches (120 to 134) and the first to fourth capacitors (1 12 to 118) are arranged in the same way as described above in relation to time interval t ₃ .

A similar calculation to that described above in relation to time interval ti, leads to the result that during the time interval t ₄ the voltage V _O p is increased

at a rate of

During time interval t ₄ the first clock signal Qi and the third clock signal Q ₃ are low. Therefore, the fourth clock signal (nQi.Q ₃ ) is low and the fifth clock signal (nQi.nQ ₃ ) is high. This results in the ninth and tenth switches (136, 138) being closed and the eleventh and twelfth switches (140, 142) being open. The first output (OP) of the OP AMP 110 is connected to the first side of the sampling capacitor 144 via the ninth switch 136 and the second output (OM) of the OP AMP 110 is connected to the second side of the sampling capacitor 144 via the tenth switch 138. The differential output voltage Vo ( V ₀ = V _OM -V _op ) is ramped up during t ₃ such that at the start of time interval t ₄ the differential output voltage V ₀ has a high value, as shown in figure 2. However, during time interval t ₄ the differential output voltage V ₀ is ramped down as shown in figure 2.

The output voltage at the end of the second period of the PWM signal T ₂ can be calculated in the same way as described above in relation to that at the end of the first period of the PWM signal T ₁ , such that:

Y _ τ/- ΠT ¹ I ¹ I ^V ' ^NT I V T\ ^{1 1} I i F

^IN [R _x C, R ₂ C ₄ ) R ₂ C ₄ ^C [R ₂ C ₄ R ₁ Cj ^0FF where the time interval t ₃ has a duration DT and the time interval t ₄ has a duration (1-D)T. During the third time period of the PWM signal T ₃ , the PWM signal is high for a time interval ts and low for a time interval tβ as shown in figure 2. During time t ₅ , the first and third clock signals (Qi and Q ₃ ) are high, whilst the second clock signal (Q ₂ ) is low.

Since the first clock signal Qi is high during the time interval t ₅ , the ninth to twelfth switches (136 to 142) are open and the thirteenth and fourteenth switches (146, 148) are closed. In this way the sampling capacitor 144 is disconnected from the outputs of the OP AMP 110. Furthermore, the first side of the sampling capacitor 144 is connected to the reference voltage V _ref via the fourteenth switch 148 and the second side of the sampling capacitor 144 is connected to the buffer 150 via the thirteenth switch 146. In this way, the voltage held at the sampling capacitor 144 at the end of time interval t ₄ is passed to the hold capacitor 152 via the buffer 150. The voltage passed to the hold capacitor 152 is held at the hold capacitor for the duration of the third period of the PWM signal T ₃ as represented by V _H in Figure 2.

During the time interval t ₅ the output of the xOR gate 102 is low, such that a low voltage is supplied to the first resistor 106 and a high voltage is supplied to the second resistor 108. For example, the voltage supplied to the second resistor 108 has a value V| _N relative to the voltage supplied to the first resistor 106.

Since the second clock signal Q ₂ is low during time interval t ₅₎ the first, second, third and fourth switches (120, 122, 124, 126) are closed and the fifth, sixth, seventh and eighth switches (128, 130, 132, 134) are open, such that the first capacitor 112 is connected between the first output (OP) and the first input of the OP AMP 110, and the second capacitor 114 is connected between the second output (OM) and the second input of the OP AMP 110. The third capacitor 116 and the fourth capacitor 118 are short-circuited by closing the second and fourth switches 122, 126 such that the third and fourth capacitors 116, 118 are discharged during time interval t ₅ . As described above, the first and second capacitors (112 and 114) are discharged during the second time period of the PWM signal T ₂ . This means that at the start of time interval t ₅ there is substantially a zero voltage difference across the first and second capacitors (112, 114). The voltage V _O p at the first output of the OP AMP 1 10 is given by:

V _0P const , and the voltage VQM at the second output of the OP AMP 110 is given by:

V ' IN - V ' r

V O _n M _tJ = Vr - ¹ + const .

R ₀ C ₀

During time interval tβ, the first and second clock signals (Qi and Q ₂ ) are low whilst the third clock signal Q ₃ is high. The result of this is that the output of the xOR gate 102 is high, such that a high voltage is supplied to the first resistor 106 and a low voltage is supplied to the second resistor 108. For example, the voltage supplied to the first resistor 106 has a value VIN relative to the voltage supplied to the second resistor 108.

As the second clock signal Q ₂ is low, the first to eighth switches (120 to 134) and the first to fourth capacitors (112 to 118) are arranged in the same way as described above in relation to time interval t ₅ .

V V

During the time interval tβ the voltage V _O p is decreased at a rate of IN -

R ₁ C ₁

and V _O M is increased at a rate of

During time interval tβ the first clock signal Qi is low and the third clock signal Q ₃ is high. Therefore the fourth clock signal (nQi.Q ₃ ) is high and the fifth clock signal (nQi.nQ ₃ ) is low. This results in the ninth and tenth switches (136, 138) being open and the eleventh and twelfth switches (140, 142) being closed. The first output (OP) of the OP AMP 110 is connected to the second side of the sampling capacitor 144 via the eleventh switch 140 and the second output (OM) of the OP AMP 110 is connected to the first side of the sampling capacitor 144 via the twelfth switch 142. The differential output voltage Vo across the sampling capacitor 144 is given by the voltage difference between the two outputs of the OP AMP 110 (i.e. V ₀ = V _0P - V _0M ). The difference between V _O p and V _O M is ramped up during t ₅ such that at the start of time interval t ₆ the differential output voltage Vo has a high value, as shown in figure 2. However, during time interval t ₆ the differential output voltage V ₀ is ramped down as shown in figure 2.

The output voltage at the end of the third period of the PWM signal T ₃ is given by:

V ^y 03 - ~ V ^y OP — V ^y OM

U ₁ C ₁ R ₂ C ₂ ) ^y ' { R ₁ C ₁ R ₂ C ₂ J where the time interval t ₅ has a duration DT and the time interval tβ has a duration (1-D)T. It should be noted that during the third period of the PWM signal the outputs of the OP AMP 110 are interchanged (as compared to during the first period of the PWM signal Ti) with regards to which side of the sampling capacitor 144 they are connected to. This swapping of the outputs is effected by closing the eleventh and twelfth switches (140, 142) during the third time period of the PWM signal T ₃ (rather than closing the ninth and tenth switches 136, 138 which is done during the first time period of the PWM signal T-i). This exchange of the outputs of the OP AMP 110 means that the offset voltage V _O FF of the OP AMP 110 occurs as a positive term in the equation for Voi and occurs as a negative term in the equation for V ₀₃ .

During the fourth time period of the PWM signal T ₄ , the PWM signal is high for a time interval t ₇ and low for a time interval t ₈ as shown in figure 2. During time interval t ₇ , the first, second and third clock signals (Qi, Q ₂ and Q ₃ ) are high. Since the first clock signal Qi is high during the time interval t ₇ , the ninth to twelfth switches (136 to 142) are open and the thirteenth and fourteenth switches (146, 148) are closed. This means that the sampling capacitor 144 is disconnected from the outputs of the OP AMP 110. Furthermore, the first side of the sampling capacitor 144 is connected to a reference voltage V _ref via the fourteenth switch 148 and the second side of the sampling capacitor 144 is connected to the buffer 150. In this way, the voltage held at the sampling capacitor 144 at the end of time interval tβ is passed to the hold capacitor 152 via the buffer 150. The voltage passed to the hold capacitor 152 is held at the hold capacitor for the duration of the fourth time period of the PWM signal T ₄ as represented by V _H in Figure 2.

The average of the output voltage V _O i at the end of the first time period of the PWM signal Ti and the output voltage V _O3 at the end of the third time period of the PWM signal T ₃ is given by:

' on ⁼ T v o\ ⁺ ^ oi )

It can be seen that by taking the average of the output voltage at the end of the first and third time periods of the PWM signal, the offset voltage V _O FF is substantially eliminated from the output voltage. This is due to the swapping of the outputs of the OP AMP 110 in relation to the sampling capacitor 144 as

described above. Furthermore, the factor substantially eliminates from the output voltage the effect of mismatch between the values of Ri and R ₂ and between the values of Ci and C ₂ .

It can also be seen that the average output voltage V013 is proportional to the duration of the PWM signal, i.e. the duty cycle of the PWM signal, D. For D=O.5 the average of the output voltage is zero.

During time interval t ₇ the output of the xOR gate 102 is low, such that a low voltage is supplied to the first resistor 106 and a high voltage is supplied to the second resistor 108. For example, the voltage supplied to the second resistor 108 has a value VIN relative to the voltage supplied to the first resistor 106.

During time interval t ₇ the second clock signal Q ₂ is high such that the first, second, third and fourth switches (120, 122, 124, 126) are open, and the fifth, sixth, seventh and eighth switches (128, 130, 132, 134) are closed. Therefore, during time period t ₇ the third capacitor 116 is connected between the first output (OP) and the first input of the OP AMP 110, and the fourth capacitor 118 is connected between the second output (OM) and the second input of the OP AMP 110. The first capacitor 112 and the second capacitor 114 are short-circuited by closing the sixth and eighth switches 130, 134 such that the first and second capacitors 112, 114 are discharged during time period t ₇ .

As described above, the third and fourth capacitors (116 and 118) are discharged during the third time period of the PWM signal T ₃ . This means that at the start of time interval t ₇ there is substantially a zero voltage difference across the third and fourth capacitors (116, 118). During the time interval t ₇ the voltage V _O p is given by:

V _0P = V _c + ( - V ^ _c - λ \t + const ,

and the voltage V _0M is given by:

V _0M = V _c -[^Ξ^)t ₊ const.

Therefore, during time interval t ₇ Vop is increased at a rate of VOM

is decreased at a rate of

During time interval tβ, the first clock signal (Qi) is low whilst the second and third clock signals (Q ₂ and Q ₃ ) are high. The result of this is that the output of the xOR gate 102 is high, such that a high voltage is supplied to the first resistor 106 and a low voltage is supplied to the second resistor 108. For example, the voltage supplied to the first resistor 106 has a value VIN relative to the voltage supplied to the second resistor 108.

Similarly to during time interval t ₇₎ during time interval t ₈ the second clock signal Q ₂ is high. This means that the first to eighth switches (120 to 134) and the first to fourth capacitors (112 to 118) are arranged in the same way as described above in relation to time interval t ₇ .

A similar calculation to that described above in relation to time interval t-i, leads to the result that during time interval t ₈ , Vop is decreased at a rate of

and V _O M is increased at a rate of

During time interval t ₈ the first clock signal Qi is low and the third clock signal Q ₃ is high. Therefore, the fourth clock signal (nQ-|.Q ₃ ) is high and the fifth clock signal (nQi.nQ ₃ ) is low. This results in the ninth and tenth switches (136, 138) being open and the eleventh and twelfth switches (140, 142) being closed. The first output (OP) of the OP AMP 110 is connected to the second side of the sampling capacitor 144 via the eleventh switch 140 and the second output (OM) of the OP AMP 110 is connected to the first side of the sampling capacitor 144 via the twelfth switch 142. The differential output voltage V ₀ across the sampling capacitor 144 is given by the voltage difference between the two outputs of the OP AMP 110 (i.e. V ₀ = V _0P -V _0M ). The difference between V _O p and V _0M is ramped up during t ₇ such that at the start of time interval t ₈ the differential output voltage V ₀ has a high value, as shown in figure 2. However, during time interval t ₈ the differential output voltage V ₀ is ramped down as shown in figure 2.

The output voltage at the end of the fourth time period of the PWM signal T ₄ is given by: . where the time interval X ₇ has a duration DT and the time interval tβ has a duration (1-D)T.

The average of the output voltages at the end of the first to fourth time periods of the PWM signal (Ti to T ₄ ) is given by: ) (V ₀ ) = V _1N T(2D -I)K

where

It can be seen that by taking the average of the output voltage at the end of the first to fourth time periods of the PWM signal the offset voltage V _O FF is substantially eliminated from the output voltage. Furthermore, the K factor substantially eliminates from the output voltage the effect of mismatch between the values of Ri and R2 and between the values of C-i, C2, C ₃ and C ₄ . In this way the offset of the OP AMP 110 and any components mismatch is eliminated by applying a chopping technique that controls the voltage supplied to the inputs of the integrator circuit in accordance with a clock derived from the PWM signal as described above.

It can also be seen that the average output voltage (V ₀ ) is proportional to the duration of the PWM signal, i.e. the duty cycle of the PWM signal, D. For D=O.5 the average of the output voltage is zero.

The cycle of operations described above over four time periods (T ₁ to T ₄ ) of the PWM signal may be repeated for every four time periods of the PWM signal that are received to reduce the effects of voltage offset and component mismatch when converting the PWM signal to a voltage output signal. However, a mismatch in the components used in the converter circuit 100 may cause a change in the value of Vc during the operation of the converter circuit 100 (i.e. during the integration time). This change in Vc may create a deviation in the output voltage, which can be expressed in the worst case by: The deviation (ΔVo) is usually very small.

The deviation in the output voltage (ΔVo) may be avoided in a second embodiment of the invention by replacing the matched first and second resistors (106, 108) with matched first and second current sources. A converter circuit 300 according to the second embodiment is shown in Figure 3.

The converter circuit 300 shown in Figure 3 has many corresponding components to those of the converter circuit 100 shown in figure 1 , which are labelled with corresponding reference numerals and are not discussed further here in relation to the second embodiment shown in figure 3.

The converter circuit of figure 3 does not include the xOR gate 102, inverter 104, first resistor 106 or the second resistor 108 of the first embodiment shown in figure 1. Instead the converter circuit 300 of the second embodiment comprises a second xOR gate 302, a second inverter 304, a first current source 306, a second current source 308, a fifteenth switch 310, a sixteenth switch 312, a seventeenth switch 314 and an eighteenth switch 316.

The PWM input signal is coupled to a first input of the second xOR gate 302. The third clock signal Q ₃ is coupled to a second input of the second xOR gate 302. The output of the second xOR gate 302 is coupled to an input of the second inverter 304. An output of the first current source 306 is coupled to the fifteenth switch 310 and to the seventeenth switch 314. An output of the second current source 308 is coupled to the sixteenth switch 312 and to the eighteenth switch 316. The first input of the OP AMP 110 is coupled to the fifteenth switch 310 and to the eighteenth switch 316. The second input of the OP AMP 110 is coupled to the sixteenth switch 312 and to the seventeenth switch 314. The fifteenth and sixteenth switches 310,312 are operated in accordance with the output of the second xOR gate 302. The seventeenth and eighteenth switches 314,316 are operated in accordance with the output of the second inverter 304.

In operation, when the output of the second xOR gate 302 is high the first current source 306 is connected to the first input of the OP AMP 110 and the second current source 308 is connected to the second input of the OP AMP 110. When the output of the second xOR gate 302 is low the second current source 308 is connected to the first input of the OP AMP 110 and the first current source 306 is connected to the second input of the OP AMP 110. The remainder of the converter circuit 300 is operated in the same way as the converter circuit 100 described above.

γ

The current sources are matched such that J ₁ = -/, = - ^M - , where \- _\ is the

R current produced by the first current source 306, I ₂ is the current produced by the second current source 308 and R=R ₁ =R ₂ . Any mismatch in the first and second current sources 306, 308 may be cancelled in the same way that the mismatch in the first and second resistors 106, 108 is cancelled as described above.

Figures 4 to 6 show simulations of values of various parameters of the converter circuit for different input PWM signals. In particular, figure 4 shows simulation graphs for the converter circuit of an embodiment in which D=O.5,

V _off =5mV, ΔR=0.1 R and ΔC=0.1 C. It can be seen that since D=0.5 the average of the output voltage VH is approximately equal to the reference voltage level V _rβf . The slight fluctuations in V _H between different time periods of the PWM signal can be seen due to component mismatch and/or an OP

AMP offset, but the average of VH substantially eliminates these fluctuations. Figure 5 shows simulation graphs for the converter circuit of an embodiment in which D=0.6, V _Off =5mV, ΔR=0.1 R and ΔC=0.1C. It can be seen that since D is greater than 0.5 the average output voltage level VH is positive (i.e. above the reference voltage V _ref ) in accordance with the equation for (V ₀ ) above. The output voltage VH is positive because the PWM signal is high for a longer time interval than it is low. This results in the output voltage Vo of the OP AMP 110 ramping up for longer than it is ramped down over a time period of the PWM signal. Therefore the output voltage at the end of a time period of the PWM signal has a positive value.

Figure 6 shows simulation graphs for the converter circuit of an embodiment in which D=O.4, V _Off =5mV, ΔR=0.1 R and ΔC=0.1C. It can be seen that since D is less than 0.5 the average output voltage level VH is negative (i.e. below the reference voltage V _ref ) in accordance with the equation for (V ₀ ) above. The output voltage VH is negative because the PWM signal is high for a shorter time interval than it is low. This results in the output voltage V ₀ of the OP AMP 110 ramping up for less time than it is ramped down over a time period of the PWM signal. Therefore the output voltage at the end of a time period of the PWM signal has a negative value.

It will be appreciated that the above embodiments are described only by way of example. Other applications and configurations may be apparent to the person skilled in the art given the disclosure herein. The scope of the invention is not limited by the described embodiments, but only by the following claims.