Title:
A manufacturing method of a transistor, a manufacturing method of an amplifier
Document Type and Number:
Japanese Patent JP6179158
Kind Code:
B2
Abstract:
A method of manufacturing a transistor with suppressed characteristic variations caused by gate current, and a method of manufacturing an amplifier using such a transistor are provided. The transistor includes a SiC substrate, an AlGaN barrier layer, and a GaN buffer layer grown on the SiC substrate, a source electrode and a drain electrodes located on the AlGaN barrier layer, and a gate electrode connected to the AlGaN barrier layer via a Schottky junction. In a burn-in step, a gate voltage is applied to the transistor to cause a drain current Id to flow, and a drain voltage is applied to the transistor to heat the transistor to reduce the gate current of the transistor compared to the gate current before the burn-in.
Inventors:
Hajime Sasaki
Application Number:
JP2013066674A
Publication Date:
August 16, 2017
Filing Date:
March 27, 2013
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/338; G01R31/26; H01L29/778; H01L29/812
Domestic Patent References:
| JP2008130949A | ||||
| JP2009507396A | ||||
| JP58038876A | ||||
| JP3089528A |
Foreign References:
| US20090173951 |
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Yoshimi Kuno
Hideki Takahashi
Yoshimi Kuno