Title:
【発明の名称】エピタキシャル層の変動の影響を受けにくい縦形MOSFET
Document Type and Number:
Japanese Patent JP2000506677
Kind Code:
A
Abstract:
A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.
Inventors:
Williams, Richard Kay
Application Number:
JP53268597A
Publication Date:
May 30, 2000
Filing Date:
March 14, 1997
Export Citation:
Assignee:
SILICONIX INCORPORATED
International Classes:
H01L21/336; H01L29/78; H01L29/08; (IPC1-7): H01L29/78; H01L21/336
Attorney, Agent or Firm:
Youichi Oshima