PURPOSE: To decrease the number of times of writing to a memory, by adding the data part overflowed from a data bus output as a part of an address signal and delivering it to an address bus.

CONSTITUTION: An address bus 3 has a margin of 2 bits to transfer an address bus A1 of 14 bits; while a data bus 4 has a shortage of 2 bits to transfer the data (d) and D2 of 10 bits. In this connection, a data in which the address A1 is set at an upper part with lower 2 bits is produced at a register 7 of 16 bits. At the same time, a data in which a data part 4 of 2 bits in the data (d) and 2D is set at the lower part with the upper part set at 0 is produced at a register 8. The data of these registers 7 and 8 are added to each other with index to synthesize address A of 16 bits and the data (d) at a register 9. The address A and the (d) of the register 9 are fed in the form of an address 10. The address 10 is separated into the address A and the data (d). On the other hand, the data D is integrated to a data input of a memory from a register 11 in the form of a data D12.