PURPOSE: To make easily a common device look like being in an overload state with simple constitution, by providing a block control circuit section blocking a request receiving control circuit section for an indicated time only.
CONSTITUTION: When a request from each module is inhibited for a prescribed time at a prescribed period, a block time value is set to a B register 9 and a release time value is set to an I register 10 to turn on a block signal. Then, a bus-enable-FF7 and a bus block FF12 are turned on and an output of a gate B8 goes to logical 0, then request signals REQ1WREQn from each module are suppressed at a gate A6. The block time value is set to a down-counter 14 with the block signal at the same time and the counter 14 generates a carrier when the state of ALL goes to 0. The FF12 is changed to the off-state with this signal, the gate B8 goes to logical 1, and the signals REQ1WREQn are received. Further, the release time value is set to the counter 14 and when the ALL of the counter 14 goes to 0, the output of the gate B8 goes to logical 1 and the signals REQ1WREQn are suppressed.
SHIBATA HIROKI
NAKAJIMA TOSHIKI
| JPS5143610A | 1976-04-14 | |||
| JPS5588148A | 1980-07-03 |