Title:
リング周波数分割器
Document Type and Number:
Japanese Patent JP6561138
Kind Code:
B2
Abstract:
A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).
Inventors:
Mellanson, John El.
Mortazabi, Yusov
Brennan, Aaron
Mortazabi, Yusov
Brennan, Aaron
Application Number:
JP2017560815A
Publication Date:
August 14, 2019
Filing Date:
May 19, 2016
Export Citation:
Assignee:
Cirrus Logic International Semiconductor Limited
International Classes:
H03K23/58; H03L7/099; H03L7/24
Domestic Patent References:
| JP10093396A |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Natsuki Morishita
Takatoshi Iida
Daisuke Ishikawa
Kensaku Yamamoto
Natsuki Morishita
Takatoshi Iida
Daisuke Ishikawa
Kensaku Yamamoto