To provide a TDC capable of eliminating a need for correcting a digital code for the purpose of compensating variation in delay time of a delay element.
A PLL circuit has: an oscillation part outputting an output signal having a frequency which is a desired multiple of a frequency of a reference signal; and a phase comparator calculating a difference with respect to a sum of integer frequency division and decimal frequency division of the output signal for the reference signal and to the desired multiple, and making the oscillation part output the output signal so as to make the difference become zero. In the PLL circuit, a TDC 2 has: a digital code generator 23 setting an initial value of the decimal frequency division and outputting the initial value as a measurement value; and the digital code generator 23 and an addition and subtraction unit 24, after operations of the phase comparator and the oscillation part based on the initial value, updating the decimal frequency division from the initial value to an optimum value in a step-wise manner using resolution of the decimal frequency division as one step, in a direction that makes the difference become zero, and outputting the optimum value as the measurement value.
MOROHOSHI MITSUNORI
NATSUME KAZUNUSHI
KIMURA MASAHO
