Title:
PI3 DEVICE AND METHOD
Document Type and Number:
Japanese Patent JP3856846
Kind Code:
B2
Abstract:
PURPOSE: To prevent the damage of a dielectric by a method wherein a wafer is supported on the first electrode in a low pressure chamber, and a high voltage pulse is applied to the first electrode, so that cold cathode plasma with a short sustaining time is induced in the neighborhood of an electrode of the wafer.
CONSTITUTION: A wafer 6 is shielded by a cylindrical wall 5 connected to a wall in a chamber 9, and a high voltage power source 3 is connected to an electrode 4. A negative pulse is applied to a cold cathode 7 from a power source PS2, and is applied to the wafer 6. The power sources 2, 3 take a timing by a trigger so that a synchronized pulse can be precisely obtained. A pulsed negative voltage applied to the electrode 4 forms lines of electric force from the electrode 4 to a chamber wall with the same potential. Since all of the lines of electric force are focused on the surface of the electrode 4, electrons in the neighborhood of the wafer 6 is stripped from gas when the pulse is applied. This is formed in the area, positive ions which are slower in movement are left behind, and these ions are accelerated next and injected into the wafer 6.
Inventors:
Terry Thien You Sheng
Application Number:
JP11169194A
Publication Date:
December 13, 2006
Filing Date:
April 28, 1994
Export Citation:
Assignee:
Varian Semiconductor Equipment Associates, Inc.
International Classes:
C23C14/48; H01L21/265; H01J27/02; H01J37/317; H01J37/32; (IPC1-7): H01J37/317; C23C14/48; H01J27/02; H01L21/265
Domestic Patent References:
| JP4280055A | ||||
| JP6256943A |
Attorney, Agent or Firm:
Sumio Takeuchi
Akira Hori
Akira Hori
Previous Patent: 蒸気透過性加圧パッケージ
Next Patent: LOW-DENSITY LAMINATED THERMAL INSULATION MATERIAL AND ITS PRODUCTION
Next Patent: LOW-DENSITY LAMINATED THERMAL INSULATION MATERIAL AND ITS PRODUCTION