Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NEGATIVE-POLARITY INPUT-VOLTAGE PREVENTIVE CIRCUIT
Document Type and Number:
Japanese Patent JP2001069674
Kind Code:
A
Abstract:

To work a negative-polarity input-voltage preventive circuit, so as to obstruct the application of inverse voltage to the input to a power circuit by detecting inverse voltage, when negative-polarity voltage is applied, and to supply power circuit with input voltage in low loss, in the case of a normal voltage input also.

An MOS FET 3 is inserted between an input terminal and an output terminal, a transistor 9 detecting inverse voltage applied to a primary power line is installed, a bias voltage is applied to resistance voltage dividers 8, 13 between a gate and a source for the MOS FET 3, so as to make the MOS FET 3 conductive in the case of normal polarity application, and the MOS FET 3 is turned on. The MOS FET 3 is brought to a discontinuity state by the transistor 9 in the case of the application of reverse polarity, and the MOS FET 3 is turned off.


Inventors:
SHIMANUKI HIDEYA
Application Number:
JP24276699A
Publication Date:
March 16, 2001
Filing Date:
August 30, 1999
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC WIRELESS NETWORKS LTD
International Classes:
H02J7/00; H02H11/00; (IPC1-7): H02J7/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)