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Title:
MONITOR CIRCUIT FOR MONITORING FINAL STAGES OF PLURAL VALVES
Document Type and Number:
Japanese Patent JPH0370667
Kind Code:
A
Abstract:

PURPOSE: To perform high-reliable monitoring through simple constitution by connecting the work connection part of valves such as pressure control, etc., of an anti-lock control system to a comparator circuit and an OR link to evaluate these outputs depending on a test pulse.

CONSTITUTION: In a monitor circuit used to the pressure control valves (W1-W4) of an anti-lock control system, each one power transistor LT1-LT4 is provided to each final driver for changing each pressure control value. Control signals from a controller are applied to connection parts E1-E4 led to the gates of the transistors LT1-LT4. The work connection parts S1-S4 of the respective control valves are connected to output A1 by the XOR1-XOR3 (exclusive OR) of a comparator circuit 1. The bases of the transistors T1-T4 of an OR link 2 are connected to the connection parts S1-S4, and the output A2 of a transistor T6 to be connected to these emitter sides, together with the output A1, is inputted to an XOR4.


Inventors:
HANSUUBIRUHERUMU BURETSUKUMAN
HAINTSU RORETSUKU
MIHIAERU TSUIDEKU
Application Number:
JP20495990A
Publication Date:
March 26, 1991
Filing Date:
August 01, 1990
Export Citation:
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Assignee:
TEVES GMBH ALFRED
International Classes:
B60R16/02; B60T8/32; B60T8/36; B60T8/90; B60T17/22; G01R31/00; G01R31/28; G05B23/02; G01R31/06; H01F7/18; H03K19/00; (IPC1-7): B60R16/02; B60T8/36; B60T8/90; G01R31/06; G01R31/28; G05B23/02; H01F7/18; H03K19/00
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)



 
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