Title:
半導体装置の作製方法
Document Type and Number:
Japanese Patent JP5530687
Kind Code:
B2
Abstract:
To reduce current consumption in a frequency-division circuit, particularly in a multistage frequency-division circuit, in a multistage frequency-division circuit, an inputted signal has a higher frequency in a preceding stage, and an inputted signal has a lower frequency in a following stage. Thus, placement is performed preferentially from the basic cell corresponding to the frequency-division circuit into which a signal having a higher frequency is inputted, and then wiring connection is performed. In other words, the layout of a plurality of basic cells corresponding to a multistage frequency-division circuit is performed so that, as compared to a wiring into which a signal having a lower frequency is inputted, a wiring into which a signal having a higher frequency is inputted has a shorter wiring length and has less intersection with other wirings, so that parasitic capacitance and parasitic resistance of the wiring are reduced.
Inventors:
Tomoaki Atami
Application Number:
JP2009216312A
Publication Date:
June 25, 2014
Filing Date:
September 18, 2009
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/822; G06F1/04; G06F1/32; H01L21/82; H01L27/04; H03K23/00
Domestic Patent References:
| JP9245065A | ||||
| JP2002217710A | ||||
| JP4239222A | ||||
| JP2007294484A | ||||
| JP5041660A |