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Patent Searching and Data


Title:
DELAY CIRCUIT
Document Type and Number:
Japanese Patent JP2010050516
Kind Code:
A
Abstract:

To provide a delay circuit of a lamp waveform generation system, capable of shortening a time required for reset operation, corresponding to a high speed repeated input signal by suppressing noise that occurs during the reset operation and achieving high integration and low power consumption.

The delay circuit includes: a delay generation capacitance for generating a lamp waveform; a first switch, one end of which is connected to a first initial voltage generator and the other end of which is connected to one end of the delay generation capacitance; a second switch, one end of which is connected to a second initial voltage generator and the other end of which is connected to the one end of the delay generation capacitance; a third switch, one end of which is connected to a charge current source and the other end of which is connected to the one end of the delay generation capacitance; a fourth switch, one end of which is connected to a discharge current source and the other end of which is connected to the one end of the delay generation capacitance; a first comparator; a first one shot whose input an output of the first comparator is connected to; a second comparator; a second one shot whose input an output of the second comparator is connected to; and an OR gate for outputting a delay output signal.


Inventors:
KONO ATSUSHI
Application Number:
JP2008210523A
Publication Date:
March 04, 2010
Filing Date:
August 19, 2008
Export Citation:
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Assignee:
YOKOGAWA ELECTRIC CORP
International Classes:
H03K5/13; G01R31/28; H03K3/02; H03K4/02