Title:
クロック生成回路、シリアル・パラレル変換回路及び情報処理装置
Document Type and Number:
Japanese Patent JP6819327
Kind Code:
B2
Abstract:
A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.
Inventors:
Liang Joshua
Sheikh Horace Lami Ali
Yuki Ogata
Yasutaka Tamura
Sheikh Horace Lami Ali
Yuki Ogata
Yasutaka Tamura
Application Number:
JP2017018948A
Publication Date:
January 27, 2021
Filing Date:
February 03, 2017
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L7/033; H03H21/00; H03K5/00
Domestic Patent References:
| JP7046157A | ||||
| JP2013229835A | ||||
| JP2007193294A | ||||
| JP2016025561A | ||||
| JP2017050589A |
Foreign References:
| US20060002497 |
Other References:
Sungchun Jang et al.,An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection,IEEE Transactions on Circuits and Systems II: Express Briefs,米国,IEEE,2015年 8月28日,Year: 2015/Volume: 62/Issue: 9,pp. 836-840
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto
Koichi Itsubo
Tsutomu Kono
Tetsuo Miyamoto