Document Type and Number:
Japanese Patent JPS6141461
Kind Code:
B2
Abstract:
An apparatus for reducing a sampling frequency which derives information with the bandwidth fB/N (N is an integer) having a sampling frequency of 2fB/N from an input FDM signal with a bandwidth up to fB having the sampling frequency 2fB has been found. The present apparatus comprises a pair of partial frequency reduction systems and a switch for alternately selecting the outputs of said partial frequency reduction systems to provide the output signal. Each of said partial frequency reduction systems comprises a DFT means for performing the discrete Fourier transform for every G sampling points (G is the multiple of N) to said input signal, a multiplication means for multiplying the predetermined frequency characteristics with the output of said DFT means, linear conversion means for linear conversion of the output of said multiplication means and for providing G/N number of data, and means for performing the inverse discrete Fourier transform to the output of said linear conversion means. The present invention reduces sampling frequency by performing a smaller number of multiplications than a prior art, thus, the structure of an apparatus can be simple.
Inventors:
SAKAKI HIROSHI
SHINTANI SOTOKICHI
SHINTANI SOTOKICHI
Application Number:
JP4219278A
Publication Date:
September 16, 1986
Filing Date:
April 12, 1978
Export Citation:
Assignee:
KOKUSAI DENSHIN DENWA CO LTD
International Classes:
H04J1/10; H03K7/02; H04J3/00; H04J4/00