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WO/2020/133537A1 |
Provided is a clock domain crossing (CDC) processing circuit for processing data between asynchronous clock domains with low delay. The CDC circuit comprises a phase alignment circuit (330) and a synchronization circuit (340), wherein th...
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WO/2020/132976A1 |
Disclosed are a frequency source and a communication device. A processor in the frequency source is used for generating a target frequency and a control signal; a phase-locked loop is used for outputting a pump voltage to a loop filter f...
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WO/2020/139593A1 |
A circuit includes a first filter (402), a plurality of binary -weighted capacitors (C1, C2, Cn), and a current source device (Ml). The circuit also includes a first plurality of switches (SW3). Each of the first plurality of switches (S...
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WO/2020/129954A1 |
A ranging/imaging device (1) is provided with: a timing control unit (100) which outputs one or more timing signals; a light-receiving unit (204) which receives reflected light, due to a subject, of light emitted from a light source (203...
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WO/2020/131840A1 |
Systems and methods are provided for compensating for mechanical acceleration at a reference oscillator, A reference oscillator provides an oscillator output signal and an accelerometer on a same platform as the reference oscillator, suc...
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WO/2020/125189A1 |
A device and method for realizing data synchronization. The device comprises: a multiple radio frequency chip synchronization circuit, and/or a single-chip multi-channel synchronization circuit, wherein the multiple radio frequency chip ...
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WO/2020/129947A1 |
A DLL circuit (10) is provided with: a temporal difference amplifying circuit (11) which, with respect to a first signal and a second signal that have been input, performs a process for amplifying a temporal difference between an edge th...
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WO/2020/126454A1 |
The invention relates to a system (100) comprising: - a clocking system component (1) comprising - a micromechanical oscillating element, which can be excited to oscillate at a characteristic frequency (f_osc), and - first circuit means ...
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WO/2020/131218A1 |
Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuit...
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WO/2020/123587A1 |
A phase-locked loop (PLL) device (102 A) includes: 1) a detector (104 A) configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump (106 A) coupled to th...
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WO/2020/120497A1 |
A frequency synthesiser arrangement (100) is arranged to receive a clock input signal (116) and provide an output signal (118). The frequency synthesiser arrangement (100) comprises: a frequency divider (110) arranged to divide the outpu...
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WO/2020/123078A1 |
Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally ...
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WO/2020/123077A1 |
Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-typ...
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WO/2020/118209A1 |
A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by...
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WO/2020/113953A1 |
Techniques are described for reducing frequency pulling in voltage-controlled oscillator (VCO) circuits. Some embodiments operate in context of a transmitter having a VCO and a power amplifier (PA), where resonant components of the VCO a...
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WO/2020/115757A1 |
The present invention provides a circuit for generating a control voltage depending on voltage phase of an input signal. The circuit comprises a first transistor; a second transistor, a diode, a Zener diode and a capacitor. Base and coll...
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WO/2020/113922A1 |
Techniques are described for staggered-bias varactors. For example, a staggered-bias varactor can include a control voltage node, a number of bias voltage nodes, and a number of sub-varactors coupled in parallel. The control voltage node...
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WO/2020/112259A1 |
A circuit (30) includes a programmable frequency divider (14) which receives a high-speed clock (12), ƒin, as an input and which provides a modulated reference clock (20) as an output; a Sigma-Delta modulator (16) which receives a Frequ...
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WO/2020/112277A1 |
A PLL system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the TDC is disclosed. The system includes a phase modulation circuit configured to generate phase shifts for a reference signal; sel...
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WO/2020/108731A1 |
A pulse-width modulation signal generator (3) is described. The pulse-width modulation signal generator comprises an analogue delay-locked loop (7) which comprises a delay line (11) arranged to receive a clock signal (CLKSYS), the delay ...
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WO/2020/036560A9 |
The present invention is related to a self operating oscillator which increases an input DC voltage with a coefficient factor of 4 or more, by using a primary and a secondary LC tank in order to provide a differential sinusoidal output v...
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WO/2020/105116A1 |
A lock detection circuit (10) is configured to be provided with: an integration circuit (11) that integrates the phase difference between a frequency-divided signal and a reference signal in a VCO (5) during a particular time period with...
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WO/2020/103775A1 |
The present invention discloses a method and device for smooth transition of a reference clock under a lock state of an analog phase-locked loop. The device comprises: an input logical unit, connecting with a voltage-controlled oscillato...
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WO/2020/105182A1 |
This voltage-controlled oscillator (5) is provided with: a first transistor (M1) in which a gate is connected to an input terminal (PIN), a source is connected to a ground VSS, and a drain is connected to a first node (N1); a second tran...
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WO/2020/100135A2 |
An ECG system and a method for operating a handheld device that provides input to an ECG system are disclosed. The handheld device has a plurality of receiving channels. Each receiving channel includes an electrode that is adapted for re...
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WO/2020/094234A1 |
A signal generator (100) with direct digital synthesis and tacking filter to generate an oscillator signal is disclosed. The signal generator (100) comprises a digital signal generator (110) configured to generate a digital signal; a dig...
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WO/2020/091985A1 |
Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wher...
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WO/2020/086578A1 |
Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase mea...
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WO/2020/077558A1 |
Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to incl...
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WO/2020/076713A1 |
Methods and digital circuits provide frequency correction to frequency synthesizers. Dual switched-capacitor voltage detectors connected to an input signal periodically sample the voltage of the input signal, and then determine a fundame...
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WO/2020/077141A1 |
Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configur...
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WO/2020/075743A1 |
Provided are a gas cell and a gas cell manufacturing method with which an S/N ratio of light serving as a signal can be increased and high accuracy can be achieved. The gas cell comprises: a reflection space (14) provided so as to be cap...
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WO/2020/072165A2 |
A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a ...
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WO/2020/068206A1 |
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of tw...
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WO/2020/068292A1 |
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply...
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WO/2020/069203A1 |
A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock si...
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WO/2020/061080A1 |
To improve power converter ON-time generation, an example apparatus (300) includes a phase frequency detector (302) to determine a phase difference between a first signal (318) and a second signal (320), a first pulse generator (308) to ...
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WO/2020/060680A1 |
An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscil...
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WO/2020/059494A1 |
This oscillation circuit according to the present disclosure comprises: a current source which is connected to a connection node and capable of flowing a current having a current value according to an input voltage from a first power sup...
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WO/2020/055510A1 |
A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a r...
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WO/2020/051906A1 |
A computer readable storage medium, a quick start clock system and a control method therefor. The system comprises: a digital auxiliary circuit (200) for outputting a digital control value; a phase locked loop (300) comprising: a program...
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WO/2020/055741A1 |
An integrated circuit comprises a timebase generator (700) and a switch mode direct current-to- direct current (DC-to-DC) voltage converter coupled to the timebase generator (700). The timebase generator (700) comprises a first linear fe...
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WO/2020/055744A1 |
A circuit includes a phase and frequency detector circuit (102) to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data si...
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WO/2020/047672A1 |
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more ph...
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WO/2020/041967A1 |
A phase locked loop circuit, relating to the field of digital circuits and used for tracking and generating a clock signal. The phase locked loop circuit comprises a reference phase generating circuit and a clock signal generating circui...
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WO/2020/046503A1 |
An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first re...
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WO/2020/042888A1 |
A method and apparatus for digitizing a scintillation pulse. The method comprises: step S1: setting n theoretical threshold voltages according to a multiple-voltage threshold sampling requirement; step S2: calculating pulse width modulat...
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WO/2020/046489A1 |
Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a loca...
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WO/2020/038542A1 |
An oscillator circuitry is disclosed. The oscillator circuitry comprises an oscillator (8) for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the oscillator. The frequency a...
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WO/2020/038899A1 |
Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator (8) for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscil...
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