BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatuses and methods for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In wireless communications, there may be uplink communications from a user equipment to a base station and downlink communications from the base station to the user equipment. Wireless communications from the user equipment and from the base station may be processed in a modem or similar device that can include multiple chips coupled by one or more interfaces.

SUMMARY

[0003] Embodiments of apparatus and method for serializer/deserialization forward flow control are disclosed herein.

[0004] In one example, an apparatus for forward flow control can include a first buffer on a first chip. The apparatus can also include a second buffer on a second chip. The apparatus can further include an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer. The apparatus can additionally include a control circuit configured to perform forward flow control of data passed from the first buffer to the second buffer.

[0005] In another example, a method of forward flow control in a communication device comprising a first buffer on a first chip, a second buffer on a second chip, an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer, and a control circuit. The method can include determining a depth of data in the second buffer. The method can further include releasing data from the first buffer to the second buffer across the interface based on the determined depth.

[0006] In a further example, an apparatus for forward flow control can include a first buffer on a first chip, a second buffer on a second chip, a third buffer on the second chip, and an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer. The apparatus can also include a first control circuit configured to perform forward flow control of data passed from the first buffer to the second buffer and a second control circuit configured to provide a back pressure signal from the third buffer to the second buffer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates a typical way of using back pressure.

[0009] FIG. 2 illustrates semi-dynamic flow control according to certain embodiments of the present disclosure.

[0010] FIG. 3 illustrates depth levels, according to certain embodiments of the present disclosure.

[0011] FIG. 4 illustrates the calculation of time to send a new packet in a forward flow control scheme, according to certain embodiments of the present disclosure.

[0012] FIG. 5 illustrates the use of an accumulator in connection with certain embodiments of the present disclosure.

[0013] FIG. 6 illustrates a state machine in accordance with certain embodiments of the present disclosure.

[0014] FIG. 7 illustrates a run state of forward flow control, according to certain embodiments of the present disclosure.

[0015] FIG. 8 illustrates a method for forward flow control according to certain embodiments.

[0016] FIG. 9 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency chip, and a host chip, according to some embodiments of the present disclosure.

[0017] FIG. 10 illustrates an example node, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0018] FIG. 11 illustrates an example wireless network, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. [0019] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0021] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0022] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0023] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system. [0024] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as Global System for Mobile communication (GSM). An OFDMA network may implement a RAT, such as Long-Term Evolution (LTE) or New Radio (NR). The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0025] Serializer/DeSerializer (Ser/Des) is a term that can refer to a high-speed digital interface between a radio frequency integrated circuit (RFIC) and a baseband integrated circuit (BBIC). Examples of such interfaces that can serve as a Ser/Des include JESD204a/b/c and M- PHY from the Mobile Industry Processor Interface (MIPI) alliance. Other such interfaces are also permitted.

[0026] Depending on RFIC design, data across SerDes can be continuous or bursty. On the uplink, if bursty traffic is used, back pressure may usually be needed to regulate the flow of uplink samples across SerDes.

[0027] Sending back pressure across downlink SerDes constantly can have a number of impacts, as illustrated in the following example. FIG. 1 illustrates a typical way of using back pressure with respect to a serializer/deserializer. More specifically, FIG. 1 illustrates a way of using back pressure to regulate uplink (UL) flow.

[0028] A Tx modulator (TxMoD) can generate uplink samples and deposit them into a memory pool (MemPool) before over the air (OTA) uplink transmission starts. MemPool can be a large memory buffer on the BBIC. FIFO2 and FIFO1 can be buffers on the RFIC. Processing block is an example of uplink blocks to process and upsample uplink signals. Resampler is a block that can convert bursty incoming samples in FIFO1 into continuous outgoing samples.

[0029] Full dynamic flow control based on back pressure (BP) can work in the following way. Before OTA transmission starts, TxMoD can generate UL samples and can transmit them across SerDes and all the way to FIFO1. When FIFO1 is almost full, Back Pressure 1 (BP1) can be generated to halt samples from FIFO2. When FIFO2 is almost full, Back Pressure 2 (BP2) can be generated to halt samples from MemPool . BP2 can be sent across SerDes, which can incur delay and add additional traffic to downlink. When MemPool is almost full, Back Pressure 3 (BP3) can be generated to halt TxMoD.

[0030] Certain embodiments of the present disclosure provide a forward flow control logic on, for example, the BBIC to minimize the frequent back pressure across SerDes. Such embodiments may reduce the reliance on downlink SerDes and may increase the reliability of uplink flow control.

[0031] The use of full dynamic flow control, illustrated in FIG. 1, can have the following characteristics. When FIFO2 is almost full, BP2 needs to be generated for every uplink packet to avoid FIFO2 overflow. BP2 is sent across SerDes, which causes extra delay. Even if there is no downlink traffic, downlink SerDes needs to be kept alive to transfer BP2. This causes more power consumption. BP2 adds additional traffic to downlink SerDes. If downlink SerDes is congested or experiences any error, BP2 may not be sent to MemPool in time. This may cause too many uplink samples sent across SerDes to FIFO2. Once FIFO2 is full, any more samples have to be dropped. Dropped samples will cause catastrophic failure in the uplink. In short, there are a number of potential drawbacks associated with the use of full dynamic flow control. Certain embodiments of the present disclosure provide alternatives to full dynamic flow control.

[0032] FIG. 2 illustrates semi-dynamic flow control according to certain embodiments of the present disclosure. As shown in FIG. 2, a forward flow control logic can be provided on a chip, for example, on the BBIC, to regulate traffic across SerDes to reduce the reliance on frequent BP2 across SerDes downlink direction. Semi -dynamic flow control is shown in FIG. 2, which can be a mixture of back pressures (BP1 and BP3) and forward flow control (FFC).

[0033] In certain embodiments, FFC, which can be implemented in hardware, can be provided on BBIC and can regulate traffic across SerDes to avoid frequent BP2 transmission on downlink SerDes. FFC features can include a state machine to model several states of uplink transmission, a status register (with integer and fractional part) to represent FIFO2 level, an accumulator (with integer and fractional part) to help predict when to transmit the next packet, exception handling of FIFO2 low (RFIC knows the burst size, for example) or high, and query of FIFO2 status from time to time.

[0034] As shown in FIG. 2, there can still be the use of BP1 from FIFO1 to FIF02 and the use of BP3 from MemPool. Thus, this approach can be viewed as a hybrid form of FFC.

[0035] FIG. 3 illustrates depth levels, according to certain embodiments of the present disclosure. In particular, FIG. 3 is an illustrative depiction of a buffer, such as FIFO2 depth levels. As shown, full depth (full depth) can be the maximum amount of data that can be stored in a given buffer. Above full depth, data may be lost, as additional samples received at the buffer may simply be dropped. High depth (high depth) can refer to a high level of data stored in the buffer, at which point the full depth is coming soon. The high depth can be, for example, 80% of full depth. Target depth (target depth) can refer to a level that is considered appropriate for optimal operation. Target depth may be, for example, 60% of full depth. Low depth (low depth) can trigger the immediate transmission of a new packet. Low depth may be, for example 40% of full depth.

[0036] FFC inputs can include the various depth levels of FIFO2. There can also be other inputs. For example, the FFC can take into account resampler start time (start time) and stop time (stop time), in terms of system time clock (STC) count. FFC can also take into account sampling rate across SerDes (serdes sample rate) and BBIC clock rate (bbic clock rate), which can be the clock rate of the BBIC. Other inputs can include SerDes packet size (samples_per_packet) and FIFO2 query period (fifo_query_period) in terms of STC counts.

[0037] The precise mechanism for FFC can vary. Some other parameters that can be considered can be SerDes packet length (serdes_packet_length), which can be calculated as serdes_packet_length=samples_per_packet/serdes_sample_rate, and BBIC clock length (bbic clock length), which can be calculated as bbic_clock_length=l/bbic_clock_rate. Another parameter can be packet per BBIC clock (packet_per_bbic_clock), which can be calculated as packet_per_bbic_clock=bbic_clock_length/serdes_packet_length . The parameters can be in various formats. For example, packet _per_bbic_clock can be in U16Q15 format, which means it can be an unsigned 16 bit number, 1 integer bit, 15 fractional bit. An accumulator can accumulate packet_per_bbic_clock, every time a carry is generated, a new SerDes packet should be sent to RFIC. The timing of sending a packet can be calculated by firmware (FW).

[0038] Samples consumed from FIFO2 for every BBIC clock (transmitted_samples_per_bbic_clock) can be calculated as transmitted_samples_per_bbic_clock=serdes_sample_rate/bbic_c lock_rate. A status register can perform fifo level estimation of FIFO2 level. Both integer and fractional bits can be used to represent fifo level. In other words, fifo level may contain non-integer numbers to help count fractional samples consumed from FIFO2 for every BBIC clock.

[0039] FIG. 4 illustrates the calculation of time to send a new packet in a forward flow control scheme, according to certain embodiments of the present disclosure. As shown in FIG. 4, a counter can be kept of bbic clock length. Whenever the counter is 1 or greater (exceeds 1) then the next packet can be sent. The counter step size can be very fine. The SerDes packet length may not neatly align with the counter, and consequently, the time when a packet is sent may differ. For example, a first packet can be sent after four BBIC clock lengths, and a second packet can be sent after three BBIC clock lengths.

[0040] FIG. 5 illustrates the use of an accumulator in connection with certain embodiments of the present disclosure. As shown in FIG. 5, an accumulator can receive a packet _per_bbic_clock in U16Q15 format, and the carry bit from the accumulator can be used to indicate the time to send a new packet.

[0041] FIG. 6 illustrates a state machine in accordance with certain embodiments of the present disclosure. As shown in FIG. 6, a state machine can include support for at least three states: initial state, run state, and stop state. Initial state can be the state of the FFC before a start time (start time). Run state can be the state of the FFC after a resampler starts, but before the last packet is sent. Stop state can be the state of the FFC after the last packet is sent.

[0042] More particularly, in initial state, at least one symbol of UL sample(s) may be ready in MemPool . The fifo_level=0. In this state, as long as fifo level < target depth, the system can transmit one packet and update fifo level = fifo level + samples _per_packet. The system can then wait for start time

[0043] FIG. 7 illustrates a run state of forward flow control, according to certain embodiments of the present disclosure. As shown in FIG. 7, in run state, after the resampler starts, based on sample rate, the FFC can decide how often to transmit one packet to maintain Target Depth.

[0044] In time division duplex (TDD) mode, uplink may only happen for several symbols out of total 14 symbols per slot. The start and stop of uplink transmission per slot can be identified by start time and stop time. The stc counter can be compared against start time and stop time to decide if samples are consumed from FIFO2.

[0045] To regulate packet flow, for every BBIC clock, FFC can increment the accumulator by packet _per_bbic_clock. If stc counter > start time & stc counter < stop time, then fifo level = fifo level - transmitted samples _per_bbic_clock (samples consumed per bbic clock).

[0046] For every carry bit generated on packet_per_bbic_clock accumulator, FFC can instruct to send one packet and can update fifo level = fifo level + samples_per packet (packet sent). [0047] Exception handling can also be performed. If fifo level < low depth, then FFC can immediately send an additional new packet and update fifo level = fifo level + samples _per_packet. On the other hand, if fifo level > high depth, then FFC can skip the next scheduled packet and update fifo level = fifo level - samples_per packet (packet consumed).

[0048] In stop state, FFC can transmit the last packet of samples from MemPool for current UL transmission (every slot in TDD). Zero padding (adding zeroes to the end) may be needed to form a full packet. FFC can then stop and wait for the next initial state.

[0049] FFC can update fifo level every stc_counts_per_packet. For example, fifo level = fifo level - samples _per packet (packet consumed), and if fifo level <= 0, stop and wait for next initial state.

[0050] The update of fifo level can be performed in various ways under various conditions or circumstances. For example, in a normal condition, there may be no need to update fifo level. In this case, based on a new carry bit from the accumulator, one packet may be injected via SerDes to FIFO2, and one packet may be consumed from FIFO2.

[0051] FIFO2 can be queried regarding FIFO2 status periodically. For example, FFC can query FIFO2 status every fifo query period. FFC can then update fifo level based on query results.

[0052] If FIFO2 reaches high depth, an alert packet (with current fifo level) can be sent to FFC immediately. In this case, FFC can stop sending the next scheduled packet and fifo level can be updated to the current fifo level.

[0053] If FIFO2 reaches low depthm an alert packet (with current fifo level) can be sent to FFC immediately. In this case, FFC can immediately send one or more packet(s) and fifo level can be updated to the current fifo level. In this case, the update to current fifo level can occur before sending the one or more packet(s), and the information that one or more packets was sent can be used to further update fifo level, as explained above.

[0054] Certain embodiments of the present disclosure may have various benefits and/or advantages. For example, certain embodiments may avoid constant BP2 traffic across downlink SerDes. Additionally, certain embodiments may reduce traffic on downlink SerDes. Furthermore, certain embodiments may improve the reliability of uplink flow control. Also, certain embodiments may provide an improved SerDes design.

[0055] FIG. 8 illustrates a method of forward flow control, according to certain embodiments. For example, the method of FIG. 8 in a communication device that includes a first buffer on a first chip, a second buffer on a second chip, an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer, and a control circuit, for example as illustrated in FIG. 2.

[0056] The method can include, at 810, determining a depth of data in the second buffer. This determination can be done a number of ways, as discussed above, both by predicting the depth and by receiving alerts or other periodic or aperiodic feedback regarding the depth of the second buffer.

[0057] The method can also include, at 820, releasing data from the first buffer to the second buffer across the interface based on the determined depth. The releasing of the data can be based on a comparison to at least one threshold at 815. For example, a comparison can be made to a low, target, or high level. An example of such consideration can be found in FIG. 7.

[0058] The method can further include, at 817, accounting for an operating state of the device. The releasing of the data can be contingent upon an operating state selected from an initial state, a run state, and a stop state, as described above with reference to FIG. 6.

[0059] The hardware methods and systems disclosed herein (or any software or firmware equivalents thereto), such as the system of FIG. 2 or the method illustrated in FIG. 8 may be implemented by any suitable node in a wireless network. For example, FIGs. 9 and 10 illustrate respective apparatuses 900 and 1000, and FIG. 11 illustrates an exemplary wireless network 1100, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure.

[0060] FIG. 9 illustrates a block diagram of an apparatus 900 including a baseband chip 902, a radio frequency chip 904, and a host chip 906, according to some embodiments of the present disclosure. Apparatus 900 may be an example of any suitable node of wireless network 1100 in FIG. 11, such as user equipment 1102 or network node 1104. As shown in FIG. 9, apparatus 900 may include baseband chip 902, radio frequency chip 904, host chip 906, and one or more antennas 910. In some embodiments, baseband chip 902 is implemented by processor 1002 and memory 1004, and radio frequency chip 904 is implemented by processor 1002, memory 1004, and transceiver 1006, as described below with respect to FIG. 10. In some embodiments, radio frequency chip 904 and baseband chip 902 may, in whole or in part, implement the systems and methods and generate and process the signals shown in FIGs. 2-8. For example, the SerDes interface may lie between baseband chip 902 and radio frequency chip 902 in a user equipment.

[0061] Besides the on-chip memory (also known as “internal memory” or “local memory,” e.g., registers, buffers, or caches) on each chip 902, 904, or 906, apparatus 900 may further include an external memory 908 (e.g., the system memory or main memory) that can be shared by each chip 902, 904, or 906 through the system/main bus. Although baseband chip 902 is illustrated as a standalone SoC in FIG. 9, it is understood that in one example, baseband chip 902 and radio frequency chip 904 may be integrated as one SoC; in another example, baseband chip 902 and host chip 906 may be integrated as one SoC; in still another example, baseband chip 902, radio frequency chip 904, and host chip 906 may be integrated as one SoC, as described above.

[0062] In the uplink, host chip 906 may generate raw data and send it to baseband chip 902 for encoding, modulation, and mapping. The data from host chip 906 may be associated with various Internet protocol (IP) flows. Baseband chip 902 may map those IP flows to quality of service flows and perform additional data plane management functions. Baseband chip 902 may also access the raw data generated by host chip 906 and stored in external memory 908, for example, using the direct memory access (DMA). Baseband chip 902 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 902 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 902 may send the modulated signal to radio frequency chip 904. Radio frequency chip 904, through the transmitter (Tx), may convert the modulated signal in the digital form into analog signals, i.e., radio frequency signals, and perform any suitable front-end radio frequency functions, such as filtering, up-conversion, or sample-rate conversion. Crest factor reduction may be performed at this stage by the radio frequency chip 904. Antenna 910 (e.g., an antenna array) may transmit the radio frequency signals provided by the transmitter of radio frequency chip 904.

[0063] In the downlink, antenna 910 may receive radio frequency signals and pass the radio frequency signals to the receiver (Rx) of radio frequency chip 904. Radio frequency chip 904 may perform any suitable front-end radio frequency functions, such as filtering, down-conversion, or sample-rate conversion, and convert the radio frequency signals into low-frequency digital signals (baseband signals) that can be processed by baseband chip 902. In the downlink, baseband chip 902 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 906. Baseband chip 902 may perform additional functions, such as error checking, demapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 902 may be sent to host chip 906 directly or stored in external memory 908.

[0064] As shown in FIG. 10, a node 1000 may include a processor 1002, a memory 1004, a transceiver 1006. These components are shown as connected to one another by bus 1008, but other connection types are also permitted. When node 1000 is user equipment 1102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 1000 may be implemented as a blade in a server system when node 1000 is configured as core network element 1106. Other implementations are also possible.

[0065] Transceiver 1006 may include any suitable device for sending and/or receiving data. Node 1000 may include one or more transceivers, although only one transceiver 1006 is shown for simplicity of illustration. An antenna 1010 is shown as a possible communication mechanism for node 1000. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 1000 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, network node 1104 may communicate wirelessly to user equipment 1102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 1106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0066] As shown in FIG. 10, node 1000 may include processor 1002. Although only one processor is shown, it is understood that multiple processors can be included. Processor 1002 may include microprocessors, microcontrollers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 1002 may be a hardware device having one or many processing cores. Processor 1002 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. Processor 1002 may be a baseband chip, such as baseband chip 902 in FIG. 9. Node 1000 may also include other processors, not shown, such as a central processing unit of the device, a graphics processor, or the like. Processor 1002 may include internal memory (also known as local memory, not shown in FIG. 10) that may serve as memory for L2 data. Processor 1002 may include a radio frequency chip, for example, integrated into a baseband chip, or a radio frequency chip may be provided separately. Processor 1002 may be configured to operate as a modem of node 1000, or may be one element or component of a modem. Other arrangements and configurations are also permitted.

[0067] As shown in FIG. 10, node 1000 may also include memory 1004. Although only one memory is shown, it is understood that multiple memories can be included. Memory 1004 can broadly include both memory and storage. For example, memory 1004 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 1002. Broadly, memory 1004 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. The memory 1004 can be the external memory 908 in FIG. 9. The memory 1004 may be shared by processor 1002 and other components of node 1000, such as the unillustrated graphic processor or central processing unit.

[0068] As shown in FIG. 11, wireless network 1100 may include a network of nodes, such as a UE 1102, a network node 1104, and a core network element 1106. User equipment 1102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (loT) node. It is understood that user equipment 1102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0069] Network node 1104 may be a device that communicates with user equipment 1102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Network node 1104 may have a wired connection to user equipment 1102, a wireless connection to user equipment 1102, or any combination thereof. Network node 1104 may be connected to user equipment 1102 by multiple connections, and user equipment 1102 may be connected to other access nodes in addition to network node 1104. Network node 1104 may also be connected to other UEs. It is understood that network node 1104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0070] Core network element 1106 may serve network node 1104 and user equipment 1102 to provide core network services. Examples of core network element 1106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 1106 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 1106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0071] Core network element 1106 may connect with a large network, such as the Internet 1108, or another IP network, to communicate packet data over any distance. In this way, data from user equipment 1102 may be communicated to other UEs connected to other access points, including, for example, a computer 1110 connected to Internet 1108, for example, using a wired connection or a wireless connection, or to a tablet 1112 wirelessly connected to Internet 1108 via a router 1114. Thus, computer 1110 and tablet 1112 provide additional examples of possible UEs, and router 1114 provides an example of another possible access node.

[0072] A generic example of a rack-mounted server is provided as an illustration of core network element 1106. However, there may be multiple elements in the core network including database servers, such as a database 1116, and security and authentication servers, such as an authentication server 1118. Database 1116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 1118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 1106, authentication server 1118, and database 1116, may be local connections within a single rack.

[0073] Each of the elements of FIG. 11 may be considered a node of wireless network 1100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 1000 in FIG. 10 above. Node 1000 may be configured as user equipment 1102, network node 1104, or core network element 1106 in FIG. 11. Similarly, node 1000 may also be configured as computer 1110, router 1114, tablet 1112, database 1116, or authentication server 1118 in FIG. 11.

[0074] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 1000 in FIG. 10. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disk (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0075] According to one aspect of the present disclosure, an apparatus for forward flow control can include a first buffer on a first chip. The apparatus can also include a second buffer on a second chip. The apparatus can further include an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer. The apparatus can additionally include a control circuit configured to perform forward flow control of data passed from the first buffer to the second buffer.

[0076] In some embodiments, the interface can be a serializer/deserializer interface.

[0077] In some embodiments, the first chip can be a baseband integrated circuit.

[0078] In some embodiments, the second chip can be a radio frequency integrated circuit.

[0079] In some embodiments, the control circuit can be configured to control flow of packets from the first buffer to the second buffer based on a depth of data in the second buffer.

[0080] In some embodiments, the control circuit can be configured to calculate the depth based on a plurality of parameters.

[0081] In some embodiments, the second chip can be configured to communicate a depth level to the first chip based on at least one threshold. [0082] In some embodiments, the at least one threshold can be data in the second buffer exceeding a high depth level.

[0083] In some embodiments, the at least one threshold can be data in the second buffer not exceeding a low depth level.

[0084] In some embodiments, the first chip can be configured to release one packet from the first buffer to the second buffer in response to the data in the second buffer not exceeding the low depth level.

[0085] In some embodiments, the control circuit can be further configured to provide a back pressure signal from the first buffer.

[0086] In some embodiments, the second chip can be configured to provide a back pressure signal from a third buffer on the second chip to the second buffer.

[0087] In some embodiments, the control circuit can be configured to operate according to a plurality of states.

[0088] In some embodiments, the control circuit can include an accumulator.

[0089] In some embodiments, the accumulator can be configured to predict when to transmit a next packet from the first buffer.

[0090] In some embodiments, the accumulator can be configured to output a carry bit when the next packet is to be transmitted from the first buffer.

[0091] According to another aspect of the present disclosure, a method of forward flow control in a communication device comprising a first buffer on a first chip, a second buffer on a second chip, an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer, and a control circuit. The method can include determining a depth of data in the second buffer. The method can further include releasing data from the first buffer to the second buffer across the interface based on the determined depth.

[0092] In some embodiments, the releasing the data can be based on a comparison to at least one threshold.

[0093] In some embodiments, the releasing the data can be contingent upon an operating state selected from an initial state, a run state, and a stop state.

[0094] According to yet another aspect of the present disclosure, an apparatus for forward flow control can include a first buffer on a first chip, a second buffer on a second chip, a third buffer on the second chip, and an interface between the first chip and the second chip and configured to pass data between the first buffer and the second buffer. The apparatus can also include a first control circuit configured to perform forward flow control of data passed from the first buffer to the second buffer and a second control circuit configured to provide a back pressure signal from the third buffer to the second buffer.

[0095] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0096] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0097] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0098] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, some embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0099] Although the above discussion focused on various circuits and methods that may be applicable to a radio frequency chip of a modem or other user equipment device, the same circuits and methods may be applied to other devices including, without limitation, audio processors operating on an input audio signal to provide a crest factor reduced audio signal.

[0100] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.