Title:
SERDES INTERFACE CIRCUIT AND CONTROL DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/166906
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a SerDes interface circuit and a control device which make it possible to use the same SerDes to perform data transfer at different communication rates. The present invention includes: a FIFO 31 that receives a first clock of a first frequency, first transmission data based on the first clock, and a second clock of a second frequency which is different from the first frequency, and that outputs the first transmission data on the basis of the second clock in the order of input; a flipflop 32 that captures and holds the FIFO output on the basis of the second clock; and an output state machine 33 that receives the FIFO output and the flipflop output, and on the basis of the second clock, generates parallel data in which the same data corresponding to the first transmission data is continuous.
Inventors:
HAGIHARA KEI (JP)
NAKAMA TOMOMASA (JP)
NAKAMA TOMOMASA (JP)
Application Number:
PCT/JP2021/005703
Publication Date:
August 26, 2021
Filing Date:
February 16, 2021
Export Citation:
Assignee:
FANUC CORP (JP)
International Classes:
H03M9/00; G05B19/414; G06F13/38; H04L29/08
Foreign References:
| JP2018533791A | 2018-11-15 | |||
| JP2010535453A | 2010-11-18 |
Attorney, Agent or Firm:
AOKI, Atsushi et al. (JP)
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