Title:
SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD, AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/093190
Kind Code:
A1
Abstract:
Embodiments of the present disclosure provide a semiconductor structure manufacturing method, and a semiconductor structure. The manufacturing method comprises: a substrate at least comprising mark regions and a blank region located between the mark regions; sequentially forming a target layer and a mask layer conformally covering the substrate, and etching the mask layer to obtain a plurality of first patterns and a plurality of first dummy patterns; forming a first dielectric layer at least covering the side walls of the first patterns and the first dummy patterns, and forming a filling layer, wherein the filling layer at least covers the side walls of the first dielectric layer, and fills gaps between the adjacent first patterns, between the first dummy patterns and between the first pattern and the first dummy pattern; and forming a barrier layer as a mask, etching the first dielectric layer to form second patterns located in the mark regions, and transferring the second patterns onto the target layer.
More Like This:
Inventors:
WEI XIN (CN)
ZHANG YANG (CN)
XIA YUNSHENG (CN)
ZHANG YANG (CN)
XIA YUNSHENG (CN)
Application Number:
PCT/CN2023/093988
Publication Date:
May 10, 2024
Filing Date:
May 12, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/311; H01L21/3213; H01L23/544; H10B12/00
Foreign References:
| CN115763241A | 2023-03-07 | |||
| CN113643966A | 2021-11-12 | |||
| CN105826193A | 2016-08-03 | |||
| CN114823295A | 2022-07-29 | |||
| CN108231770A | 2018-06-29 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
Download PDF:
Previous Patent: SERVER, DUAL-MEMORY PACKAGING MODULE, AND CONNECTOR
Next Patent: DEVICES AND METHODS FOR PUSCH AND DMRS TRANSMISSION
Next Patent: DEVICES AND METHODS FOR PUSCH AND DMRS TRANSMISSION