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Patent Searching and Data


Title:
SEMICONDUCTOR INTERCONNECTION STRUCTURE, FORMING METHOD THEREFOR, AND SEMICONDUCTOR PACKAGING STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/093025
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure is a semiconductor interconnection structure, comprising: a substrate, provided with a first surface and a second surface which are oppositely arranged; a plurality of conductive pillars independent of each other, which are arranged in the substrate, one of the conductive pillars extending from the first surface to the second surface, the first end of said conductive pillar being exposed from the first surface, and the second end of said conductive pillar being exposed from the second surface; and a first conductive connection pad, which is arranged on the first surface of the substrate, the first conductive connection pad comprising a mesh structure, the mesh structure comprising a plurality of first nodes, each of the first nodes being connected to the first end of one or more of the conductive pillars, or the first end of each of the conductive pillars being connected to one or more of the first nodes, and the first ends of all the conductive pillars being interconnected to each other via the first conductive connection pad. The semiconductor interconnection structure provided by the embodiments of the present disclosure has good heat dissipation performance and mechanical properties.

Inventors:
LIU CHIH-CHENG (CN)
Application Number:
PCT/CN2023/071233
Publication Date:
May 10, 2024
Filing Date:
January 09, 2023
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/768
Foreign References:
JP2003069231A2003-03-07
CN101504935A2009-08-12
CN103426847A2013-12-04
JP2002261455A2002-09-13
KR20120051807A2012-05-23
Attorney, Agent or Firm:
SHANGHAI WINSUN INTELLECTUAL PROPERTY AGENCY (CN)
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