Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/131084
Kind Code:
A1
Abstract:
With a conventional PLL circuit, circuit characteristics change dynamically due to temperature changes and degradation over time, and therefore there was the problem that it was difficult to find suitable application parameters for DAC. This PLL circuit comprises: frequency dividers for dividing oscillation signals; a phase frequency comparator for comparing a reference signal with oscillation signals divided by the frequency dividers, and outputting signals according to the difference thereof; a loop filter that blocks high frequency components of signals output by the phase frequency comparator, and outputs signals for which the high frequency components are blocked; an oscillator that changes the oscillating frequency according to the output signals of the loop filter, and outputs oscillation signals; a digital signal processor for finding the frequency of the oscillation signals; a parameter control circuit for finding control parameters on the basis of the frequency of the oscillation signal found by the digital signal processor; and a digital analog converter that outputs analog signals to the loop filter or the oscillator according to the control parameters, and corrects the time change of the oscillating frequency.
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Inventors:
YANAGIHARA YUKI (JP)
TSUTSUMI KOJI (JP)
SHIMOZAWA MITSUHIRO (JP)
TSUTSUMI KOJI (JP)
SHIMOZAWA MITSUHIRO (JP)
Application Number:
PCT/JP2017/000541
Publication Date:
July 19, 2018
Filing Date:
January 11, 2017
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03L7/197; H03C3/00; H03L7/10
Foreign References:
| JP2015115633A | 2015-06-22 | |||
| JP2012165036A | 2012-08-30 | |||
| US7015738B1 | 2006-03-21 | |||
| US8022782B2 | 2011-09-20 | |||
| JP2006136000A | 2006-05-25 |
Attorney, Agent or Firm:
MURAKAMI, Kanako et al. (JP)
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