Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/116347
Kind Code:
A1
Abstract:
A first frequency accumulator (7a) operates using, as a clock, an output signal of a variable frequency divider (3). A second frequency accumulator (7b) operates using, as a clock, a reference signal transmitted from a reference signal source (1). A comparison operation circuit (11) compares an output value of the first frequency accumulator (7a) and that of the second frequency accumulator (7b) with each other, and calculates parameters with which the comparison result is within a set value. According to the parameters outputted from the comparison operation circuit (11), a digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6).
Inventors:
TSUTSUMI KOJI (JP)
YANAGIHARA YUKI (JP)
SHIMOZAWA MITSUHIRO (JP)
YANAGIHARA YUKI (JP)
SHIMOZAWA MITSUHIRO (JP)
Application Number:
PCT/JP2016/087780
Publication Date:
June 28, 2018
Filing Date:
December 19, 2016
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03L7/089; H03C3/00; H03L7/093; H03L7/197
Foreign References:
| JP2012039551A | 2012-02-23 | |||
| US7015738B1 | 2006-03-21 | |||
| US20110090109A1 | 2011-04-21 | |||
| US20070164829A1 | 2007-07-19 |
Other References:
TSUTSUMI KOJI ET AL.: "A Fast Chirp Generation PLL-IC using Polarity Switching Loop Filter", PROCEEDINGS OF THE 2016 IEICE GENERAL CONFERENCE, 16 March 2016 (2016-03-16), pages 54
Attorney, Agent or Firm:
TAZAWA, Hideaki et al. (JP)
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