Multi-path error-correcting demodulating method and device

FIELD OF THE INVENTION

[0001] The present invention generally relates to demodulating digital signal schemes in communication systems. More specifically, the present invention is concerned with a demodulating method and device for digital signals, using multiple paths, with capabilities of error detection and correction of the digital signals.

BACKGROUND OF THE INVENTION

[0002] For many years the photonics industry has grown steadily primarily driven by the demand for complex optical functionality. But more recently the need for reducing cost has been the main driver for innovations; the cost per transmitted bit being the primary figure of merit used to measure the potential of a new technology.

[0003] Telecommunication links are limited by physical constraints coming from the production, transmission, amplification and detection of the signals. These physical constraints may cause transmission errors found at the receiver end of the link.

[0004] For binary transmission ("1" and "0"), an error is found when a

"1" is sent but a "0" is received, and vice versa. Obviously, the transmission distance and data rate are limited by the above mentioned physical constraints since a certain "maximum error rate" can be tolerated in a telecommunication system.

[0005] New types of optical fibers and amplifiers have the capability of increasing the transmission bandwidth over a longer distance but the capital investment required for installation of these fibers and amplifiers is prohibitive taking into consideration the current state of the art.

[0006] Promising new modulation formats have also been extensively investigated in the recent years to find encoding schemes more robust to physical constraints. An advantage of these technologies is that they require modifications at the transmitter and receiver only; this minimizes the installation cost and aging transmission lines can then be upgraded at low cost. Numerous encoding schemes such as differential phase-shift keying (DPSK), return to zero DPSK (RZ-DPSK), carrier-suppressed RZ (CSRZ), chirped RZ (CRZ) and others have been successfully implemented. The robustness of these formats to physical constraints has been demonstrated. For instance, DPSK signals are more resistant to the effects of the optical noise generated from amplification. Also, recent laboratory experiments have shown significantly better performance of these formats over prior technologies.

[0007] In every flavor of differential phase-shift keying (DPSK), the information is not encoded in relation with the intensity of the signal but to the difference in phase between adjacent bits. For example, a signal at a given bit may be encoded as having a phase value of 0 or π. If two adjacent bits have the same phase, the signal will be encoded as a 0. Consequently if the phase changes from 0 to π or π to 0 between two adjacent bits, the signal will be encoded as a 1. Therefore, a particularity of the DPSK encoding scheme is that information have a certain relation, meaning that different data are logically connected together, unlike intensity modulated signals. Indeed, in optical binary transmission, information is intensity encoded to create an intensity modulated signal as follows: a high intensity signal corresponds to a bit "1" and a low intensity corresponds to a bit "0".

[0008] Several other methods are commonly used to lower the error rate of a transmission link or increase the bandwidth of a communication channel without increasing the error rate. In an optical fiber channel, new types of optical fibers and amplifiers can increase the transmission bandwidth over a longer distance but the capital investment required for installation of these equipments is, as mentioned in the foregoing description, considerable. Therefore, a solution capable of improving transmission without incurring large cost overhead would be very attractive.

[0009] A technology now commonly used to correct transmission errors is forward error correction algorithms (FEC). FEC is an error correction scheme that detects and corrects transmission errors at the receiver end without calling for retransmission. With FEC, bits are added to the message prior to transmission to detect and correct errors at the receiving end. This technology is low cost and the installation cost is not significant. A drawback of this technology is that increased bandwidth is required for transmitting the added code bits, which reduces the effective bit-rate in the transmission channel and hence results in lower data transmission capacity.

[0010] Another method for improving the bit error rate (BER) is to use techniques of electronic pre-compensation. In this scheme, deleterious effects of dispersion and nonlinearity are pre-compensated, but cannot ultimately compensate for the introduction of noise in the system.

SUMMARY OF THE INVENTION

[0011] More specifically, in accordance with the present invention, there is provided a method of demodulating a modulated digital signal, comprising: splitting the digital signal to propagate the digital signal through a plurality of signal paths; in each signal path, delaying the digital signal by a

given time delay to produce a delayed version of the digital signal, the signal paths being associated with respective, different time delays; in each signal path, combining the digital signal with the version of the digital signal delayed by the given time delay associated with the signal path to produce a bit pattern; converting the bit patterns from the different signal paths to a given bit pattern; comparing the converted bit patterns from the different signal paths to detect errors; and constructing an error-corrected digital signal from the comparison of the converted bit patterns and detection of errors.

[0012] The present invention also relates to a device for demodulating a modulated digital signal, comprising: a plurality of signal paths; means for splitting the digital signal to propagate the digital signal through the plurality of signal paths; in each signal path, means for delaying the digital signal by a given time delay to produce a delayed version of the digital signal, the signal paths being associated with respective, different time delays; in each signal path, means for combining the digital signal with the version of the digital signal delayed by the given time delay associated with the signal path to produce a bit pattern; means for converting the bit patterns from the different signal paths to a given bit pattern; means for comparing the converted bit patterns from the different signal paths to detect errors; and means for constructing an error-corrected digital signal from the comparison of the converted bit patterns and detection of errors.

[0013] The present invention is further concerned with a device for demodulating a modulated digital signal, comprising: a plurality of signal paths; a divider of the digital signal to propagate the digital signal through the plurality of signal paths; in each signal path, a delayer of the digital signal by a given time delay to produce a delayed version of the digital signal, the signal paths being associated with respective, different time delays; in each signal path, a combiner of the digital signal with the version of the digital signal delayed by

the given time delay associated with the signal path to produce a bit pattern; a converter of the bit patterns from the different signal paths to a given bit pattern; a comparator of the converted bit patterns from the different signal paths for detecting errors; and a generator of an error-corrected digital signal from the comparison of the converted bit patterns and detection of errors.

[0014] The above and other objects, advantages and features of the present invention will become more apparent upon reading of the following non-restrictive description of illustrative embodiments thereof, given by way of example only with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the appended drawings:

[0016] Figure 1 is a schematic block diagram of a non-restrictive illustrative embodiment of an error-correcting demodulating device according to thp. nresfint invention:

[0017] Figure 2 is a schematic block diagram of a delay-line interferometer forming part of the error-correcting demodulating device of Figure 1 ; and

[0018] Figure 3 is a schematic block diagram of logic gates forming part of the error-correcting demodulating device of Figure 1.

DETAILED DESCRIPTION

[0019] The error-correcting demodulating method and device according to the non-restrictive illustrative embodiment of the present invention

uses channel logic gates in encoded transmission links, for example differential phase for telecommunication, along multiple paths which can correct errors without reducing the effective bandwidth of transmission. The installation cost is low and it can significantly lower the bit error rate and the cost per bit. The method and device have the advantage that they are compatible with existing transmission systems and do not prohibit the use of any other enhancing technology. Error correction schemes like FEC can still be implemented.

[0020] Differentially phase-encoded transmission (DPSK) is usually demodulated in a delay-line interferometer (DLI) at the receiver with a single bit delay to transform the phase modulated signal to an intensity modulated signal. The non-restrictive illustrative embodiment of the present invention uses a multi-path logical demodulation where the DPSK signal is split into different paths directed to different DLIs. In the example of appended Figure 1, a power divider 14 splits the DPSK digital signal 11 into a plurality of signal portions 12i, 12 ₂ , ••• . 12N, for example a number N of signal portions propagating through respective signal paths 13i, 132, ... , 13N, respectively.

[0021 ] -Still-referring-to-Figure ~1 in the respective signal paths 13i, 132 13N are supplied to respective DLIs

15i, 152 15N.

[0022] Referring to Figure 2, in the non-restrictive illustrative embodiment, each DL1 15 can be viewed as a logical XOR gate 21, in which:

[0023] - the DPSK signal portion 12 propagating through the corresponding signal path 13 is supplied to a first input 23 of the XOR gate 21 ;

[0024] - the second input 22 of the XOR gate 21 is supplied with a

delayed version of the DPSK signal portion 12, the time delay being introduced by a delay line 24 (delayer) of the delay-line interferometer 15; and

[0025] - a corresponding bit pattern 16 is outputted from the XOR gate 21 (combiner of the signal on inputs 22 and 23).

[0026] The DLIs 15 ₁₍ 152, •■■ , 15N have respective, different time delays introduced by the delay lines 24 so that a given bit of the DPSK signal in a time slot interferes with a bit in a different time slot. Simulations have shown that the bit error rate (BER) at the output of each DLI is approximately the same for time delays of one to sixteen bits. In a non-limitative example wherein N=4:

[0027] - in the delay-line interferometer 15i of the first signal path

13- ₁ , a bit (input 23 of Figure 2) in the DPSK signal portion 12i interferes with the following bit (input 22 of Figure 2) of this DPSK signal portion 12i, a suitable 1-bit time delay having been introduced by the delay line 24 (Figure 2);

[0028] - in the delay-line interferometer 15 ₂ of the second signal path

^~ T3l>raT)lt 7inpϋT2 ^" 3 ^~ 6f ^" Figϊire ^~ 2) ^~ 1frtrτe ^~ DPSK ^~ signahportion-122-interferes-with - the second following bit (input 22 of Figure 2) of this DPSK signal portion 12 ₂ , a suitable 2-bit time delay having been introduced by the delay line 24 (Figure 2);

[0029] - in the delay-line interferometer 16 ₃ of the third signal path

13 ₃ , a bit (input 23 of Figure 2) in the DPSK signal portion 12 ₃ interferes with the fourth following bit (input 22 of Figure 2) of this DPSK signal portion 12 ₃ , a suitable 4-bit time delay having been introduced by the delay line 24 (Figure 2); and

[0030] - in the delay-line interferometer 15 ₄ of the fourth signal path

13 ₄ , a bit (input 23 of Figure 2) in the DPSK signal portion 12 ₄ interferes with the following 8 ^th bit (input 22 of Figure 2) of this DPSK signal portion 12 ₄ , a suitable 8-bit time delay having been introduced by the delay line 24 (Figure 2).

[0031] Those of ordinary skill in the art will appreciate that the bit pattern 16 (Figure 2) from the XOR gate 21 and therefore from the delay-line interferometer 15 is an intensity modulated signal, more specifically the DPSK signal portion on the input 23 modulated by the delayed version of the DPSK signal portion 12 on the input 22.

[0032] Referring back to Figure 1 , the intensity modulated signals

16i, I6 ₂ , ... , 16N are detected and converted into respective logical signals (bit patterns) 18i, 18 ₂ , ... , 18 _N through respective optical detectors 17i, 17 ₂

17 _N .

[0033] Then, logic gates 19 (bit pattern converter) of Figure 1 perform an operation inverse to the operation conducted by the delay-line interferometers 15i, 15 ₂ , ... , 15N. Accordingly, the bit patterns 18i, I82, ... , 18N ^" in the different paths- are converted -to-a-given bit-patteπvwhich-means-that, at the output of the logic gates 19, the bit patterns 20i, 2O ₂ , ... , 2ON are identical except for the errors.

[0034] Referring to Figure 3, an example of logic gates 19 is illustrated.

[0035] In the case of signal path 13i, if the delay line 24 (Figure 2) has delayed the DPSK signal portion 12i by, for example, 1 bit, the logic gates 19 comprise a XOR gate 19i connected as illustrated in Figure 3 to perform on the bit pattern I81 the operation inverse to the operation performed by the

delay line interferometer "\5- _\ to obtain converted bit pattern 2O ₁ .

[0036] In the case of signal path 132, if the delay line 24 (Figure 2) has delayed the DPSK signal portion 12∑ by, for example, 2 bits, the logic gates 19 comprise XOR gate 192i and 1922 connected as illustrated in Figure 3 to perform on the bit pattern I82 the operation inverse to the operation performed by the delay line interferometer 1§ ₂ to obtain converted bit pattern 2O ₂ .

[0037] In the case of signal path 13N, if the delay line 24 (Figure 2) has delayed the DPSK signal portion 12N by, for example, X bits, the logic gates 19 comprise XOR gates 19NI, 19 _N2) ... , 19NX connected as illustrated in Figure 3 to perform on the bit pattern 18N the operation inverse to the operation performed by the delay line interferometer 15N to obtain bit patter 2ON.

[0038J The logic gates 19 (bit pattern converter) of Figures 1 and 3 is only a non-restrictive illustrative embodiment. Indeed, one of ordinary skill in the art will be capable of designing a large number of devices capable of performing the same function. Accordingly, the present invention is in no way limited by the particular embodiment of logic gates as illustrated in Figures 1 and 3.

[0039] Since the bit patterns 20i, 2O ₂ , ... , 2O _N of the different signal paths 13i, 132, ... , 13N are identical except for the errors, it is therefore possible, for example, by comparison of the bit patterns 20i, 2O ₂ , ... . 2ON of the different paths different paths 13i, 13 ₂ , ... , 13N to detect errors and correct these errors. More specifically, the bit patterns 20i, 2O ₂ , ... , 2ON of the various paths 13i, 13 ₂ , ... , 13N are compared bit by bit by a comparison and correction unit 10 to detect and correct the errors and produce an error-corrected digital signal 100.

[0040] As an example, a comparator of the unit 10 compares the first bits of all the bit patterns 20i, 20 _{2 l} ..., 2O _N to each other. If all the first bits are identical no error is detected in the bit patterns 20i, 2O ₂ 2O _N . If all the first bits of the bit patterns 20i, 2O2, ... . 2ON are not identical, the comparator detects an error. An error-corrected digital signal generator of the unit 10 then performs a majority vote. If the first bit corresponds to a "1" in most of the bit patterns 20i,20 ₂ ,..., 2ON then we conclude that the bit "1" was transmitted and the bit "0" would be disregarded in the bit patterns where the first bit was received as a "0".

[0041] The comparator of unit 10 continues the process of comparing bit by bit the bit patterns 20i,20 ₂ ,..., 2ON with the second bits, and so on until the last bits in the bit patterns have been compared. The error-corrected digital signal generator uses the result of each bit comparison to perform, if required a a majority vote and select a bit value, in view of generating the error-corrected digital signal 100 of Figure 1.

[0042] The error-correcting demodulating method and device according to the above described non-restrictive illustrative embodiment of the present invention present, amongst others, the following advantage:

[0043] - No additional bit is required for the error correction, contrary to common error correction algorithms.

[0044] - Error correction algorithms can still be used. Although these error correction algorithms offer better performance when the error rate is lower, the cumulated effect of the multi-path error correction scheme and error correction algorithms is improved over the individual contributions; more particularly, the cumulated effect presents synergy.

[0045] - No modification to the transmission link is required to use the error-correcting demodulating method and device according to the above described non-restrictive illustrative embodiment of the present invention. Only modifications at the transmitter and receiver are required. This constitutes a significant economic advantage since modifications to the transmission link can be expensive.

[0046] - The error-correcting demodulating method and device according to the above described non-restrictive illustrative embodiment of the present invention allows reduction of the installation cost of a new telecommunication system by increasing the distance before regeneration is required.

[0047] - The error-correcting demodulating method and device according to the above described non-restrictive illustrative embodiment of the present invention can also increase the reliability and performance of a transmission or communication system. An aging system can be upgraded at low cost.

[0048] - This technology is applicable not only to fiber optic communication but also to free-space optical communication, microwave communication, mobile communication, computer interconnects, or any transmission media, where differential phase shift keying or other communication scheme is implemented.

[0049] Although the error-correcting demodulating method and device has been described with reference to a non-restrictive illustrative embodiment related to DPSK optical transmission of data, it should be kept in mind that the present invention can also be applied to other types of transmission such as satellite communication, mobile communication as well as

computer interconnects.

[0050] Although the present invention has been described in the foregoing specification by means of a non-restrictive illustrative embodiment, this illustrative embodiment can be modified at will within the scope of the appended claims without departing from the spirit and nature of the present invention.