Title:
METHOD FOR KEEPING PHASES OF FREQUENCY DIVISION CLOCKS CONSISTENT AND FREQUENCY DIVISION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/121228
Kind Code:
A1
Abstract:
A method for keeping phases of frequency division clocks consistent and a frequency division circuit. The method comprises: connecting an input end D of a last-level register of a first frequency divider with an input end D of a last-level register of a second frequency divider, wherein the first frequency divider is located outside a curing module, and the second frequency divider is located inside the curing module (201); and the first frequency divider and the second frequency divider respectively performing frequency division on a source clock signal, outputting a first frequency division signal at an output end Q of the last-level register of the first frequency divider, and outputting a second frequency division signal at an output end Q of the last-level register of the second frequency divider, wherein the phase of the first frequency division signal is consistent with the phase of the second frequency division signal (202).
Inventors:
SUN HUAYI (CN)
Application Number:
PCT/CN2016/110952
Publication Date:
July 20, 2017
Filing Date:
December 20, 2016
Export Citation:
Assignee:
SANECHIPS TECH CO LTD (CN)
International Classes:
H03K23/00
Foreign References:
| CN102195638A | 2011-09-21 | |||
| CN202043094U | 2011-11-16 | |||
| CN201663588U | 2010-12-01 | |||
| US20070159226A1 | 2007-07-12 | |||
| US20060159218A1 | 2006-07-20 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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