Title:
FREQUENCY DIVISION CIRCUIT, COMMUNICATION CIRCUIT, AND INTEGRATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/239537
Kind Code:
A1
Abstract:
The present invention has: a first latch circuit (11) that has a pair of input transistors respectively having gates connected to a signal line having a first voltage supplied therethrough and has a pair of output nodes, and that has inputted thereto a single-phase clock signal; and a second latch circuit that is of an SR type, that has a set input and a reset input connected to the pair of output nodes of the first latch circuit, and that outputs a differential clock signal which corresponds to 1/2 frequency division of the clock signal. The first latch circuit alternately repeats amplification and resetting in accordance with the clock signal. During the resetting, the nodes to which the drains of the input transistors are connected are not reset, and a highly accurate frequency division differential clock signal of high-frequency can be generated without inputting the differential clock signal to the frequency division circuit.
Inventors:
KANO HIDEKI (JP)
Application Number:
PCT/JP2018/022660
Publication Date:
December 19, 2019
Filing Date:
June 14, 2018
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03K23/00
Foreign References:
| US20160142059A1 | 2016-05-19 | |||
| JP2013219543A | 2013-10-24 | |||
| US20070252630A1 | 2007-11-01 |
Attorney, Agent or Firm:
KOKUBUN, Takayoshi (JP)
Download PDF:
Previous Patent: DEVICE FOR MEASURING SPEED OF MOVING BODY, AND ELEVATOR
Next Patent: SOUND DEVICE AND PROGRAM
Next Patent: SOUND DEVICE AND PROGRAM