Title:
DIGITAL SENDER
Document Type and Number:
WIPO Patent Application WO/2023/199394
Kind Code:
A1
Abstract:
A digital sender (DS) includes: a clock generation circuit (1A) that generates a clock (CL); a delta sigma modulation circuit (1C) that generates a first delta sigma modulation signal (DL) by performing delta sigma modulation on a digital modulation signal (DG) on the basis of the clock (CL); a distribution circuit (2) that distributes the first delta signal modulation signal (DL) among multiple second delta sigma modulation signals (DL); multiple reproduction circuits (3) that retime the multiple second delta sigma modulation signals (DL); and a synthesis circuit (4) that synthesizes the retimed multiple second delta sigma modulation signals (DL) outputted from the multiple reproduction circuits (3). The loop band of the multiple reproduction circuits (3) is smaller than or equal to the loop band of the clock generation circuit (1A), and the distribution circuit (2) performs the distribution such that the multiple second delta sigma modulation signals (DL) are in phase at a carrier frequency, or the synthesis circuit (4) performs the synthesis such that the retimed multiple second delta sigma modulation signals (DL) are in phase at the carrier frequency.
More Like This:
Inventors:
HAGIWARA TATSUYA (JP)
NAKAMIZO HIDEYUKI (JP)
NAKAMIZO HIDEYUKI (JP)
Application Number:
PCT/JP2022/017546
Publication Date:
October 19, 2023
Filing Date:
April 12, 2022
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H04L27/00; H03M3/02
Domestic Patent References:
| WO2017085789A1 | 2017-05-26 | |||
| WO2017057164A1 | 2017-04-06 |
Foreign References:
| JP2013017067A | 2013-01-24 |
Attorney, Agent or Firm:
SANNO PATENT ATTORNEYS OFFICE (JP)
Download PDF: