Title:
DELAY PHASE-LOCKED LOOP, CLOCK SYNCHRONIZATION CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/031746
Kind Code:
A1
Abstract:
Provided in embodiments of the present disclosure are a delay phase-locked loop, a clock synchronization circuit and a memory. The delay phase-locked loop comprises a preprocessing module, which is configured to receive an initial clock signal, preprocess the initial clock signal and output a first clock signal; a first adjustable delay line, which is configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal; and a phase processing module, which is configured to receive a preset control code and the first target clock signal, perform delay processing on the first target clock signal on the basis of the preset control code, and output a plurality of delayed target clock signals.
Inventors:
LI SIMAN (CN)
EOM YOONJOO (CN)
EOM YOONJOO (CN)
Application Number:
PCT/CN2022/114860
Publication Date:
February 15, 2024
Filing Date:
August 25, 2022
Export Citation:
Assignee:
CXMT CORP (CN)
International Classes:
H03L7/081
Foreign References:
| US20100103746A1 | 2010-04-29 | |||
| CN113674779A | 2021-11-19 | |||
| CN103441757A | 2013-12-11 | |||
| CN113098499A | 2021-07-09 | |||
| US20060103566A1 | 2006-05-18 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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