Title:
COMPUTATION CIRCUIT UNIT, NEURAL NETWORK COMPUTATION CIRCUIT, AND METHOD FOR DRIVING NEURAL NETWORK COMPUTATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/171406
Kind Code:
A1
Abstract:
A neural network computation circuit for outputting output data (y) in accordance with the result of sum-of-product computation of input data (x1 to xn) and connection weight coefficients (w1 to wn), wherein a computation circuit unit (PU1) that expresses one connection weight is provided with a plurality of selection transistors (TPU1, TPL1, TNU1, TNL1) and a plurality of nonvolatile variable-resistance elements (RPU1, RPL1, RNU1, RNL1), and the variable-resistance elements express weight coefficients with different weights. Each of the variable-resistance elements (RPU1, RPL1, RNU1, RNL1) holds information pertaining to high-order digits for the absolute value of a positive weight coefficient, information pertaining to low-order digits for the absolute value of the positive weight coefficient, information pertaining to high-order digits for the absolute value of a negative weight coefficient, and information pertaining to low-order digits for the absolute value of the negative weight coefficient.
Inventors:
AWAMURA SATOSHI
NAKAYAMA MASAYOSHI
NAKAYAMA MASAYOSHI
Application Number:
PCT/JP2023/006677
Publication Date:
September 14, 2023
Filing Date:
February 24, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
G06G7/60; G06G7/16; G06G7/163; G06N3/063
Domestic Patent References:
| WO2019049741A1 | 2019-03-14 | |||
| WO2022003957A1 | 2022-01-06 | |||
| WO2019188252A1 | 2019-10-03 |
Foreign References:
| JP2018120433A | 2018-08-02 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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