CHIP ENCAPSULATION STRUCTURE, CHIP ENCAPSULATION METHOD, AND ELECTRONIC DEVICE

WIPO Patent Application WO/2022/241623

A1

A chip encapsulation structure, comprising a substrate, a bare chip mounted upside down on the substrate, at least one conductive bump located between the substrate and the bare chip, and a conductive sealing ring. A functional element is arranged on the surface of the bare chip that faces the substrate. The conductive bump is electrically connected to the bare chip and the substrate. The functional element and the substrate are spaced apart from each other by means of the sealing ring, and the sealing ring surrounds the functional element to form a closed ring shape, so that a closed cavity is formed between the substrate and the bare chip. Further provided in the present application are an electronic device to which the chip encapsulation structure is applied, and a preparation method for the chip encapsulation structure. According to the chip encapsulation structure of the present application, in a space where the conductive bump originally needs to be arranged between the bare chip and the substrate to realize electrical connection between the bare chip and the substrate, the sealing ring in a closed ring shape is arranged, such that the closed cavity is formed between the bare chip and the substrate to avoid damage to the functional element, thereby simplifying the chip encapsulation structure.

CHEN CHIENHUA (CN)
LIN LAICUN (CN)
ZHANG SHAN (CN)
LIU GUOWEN (CN)

PCT/CN2021/094189

November 24, 2022

May 17, 2021

Click for automatic bibliography generation  

HUAWEI TECH CO LTD (CN)

H03H9/25; H01L41/053

US20040100164A1	2004-05-27
CN1476166A	2004-02-18
US20030000067A1	2003-01-02
CN102842531A	2012-12-26

SHENZHEN SCIENBIZIP INTELLECTUAL PROPERTY AGENCY CO., LTD. (CN)

View/Download PDF      PDF Help

Previous Patent: METHODS AND APPARATUS FOR DETERMINING DISCOVERY BURST TRANSMISSION WINDOW, AND STORAGE MEDIUM

Next Patent: PERFORMING SECURITY UPDATES WITHOUT RESYNCHRONIZATION