CHANNEL HIGH SPEED DEVICES

TECHNICAL FIELD

[0001] This disclosure relates to clock generation circuits. More specifically, this disclosure relates to low power clock generation.

BACKGROUND

[0002] The requirements for low power clock generation at higher rates in wireline transceivers increase directly with the ever-increasing baud rates associated with evolving generations of digital communications systems and the need for low power transceivers for data center interconnects. One example is optical coherent modems, which are foundational to achieving transport speeds of 100G and beyond, delivering Terabits of information. In addition to increased baud rate for a single channel, optical coherent modems are composed of multiple (typically four) channels. All channels must operate in synchronicity with each other and have equal bit delays. The nature of multiple channel modems makes it especially important that the transmitter (Tx) startup clock phases be aligned across all channels while the total power used to generate the clocks be as low as possible.

SUMMARY

[0003] Described herein are apparatus and methods for low power clock generation in multichannel high speed devices.

[0004] In implementations, a multi-channel data processing system includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (Fs)(Fs/N) clock, where N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the Fs/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.

[0005] In implementations, the channel local clock generation circuit further including a multi-phase clock generator configured to generate multiple Fs/N frequency clocks with different phases for each input port. In implementations, the different phases are 1/Fs apart. In implementations, a number of the multiple Fs/N frequency clocks is dependent on a timing margin needed by a data processing channel to process input data. In implementations, each data processing channel further including a multiplexor associated with each input port, and a multiphase clock generator connected to each multiplexor, the multi-phase clock generator configured to generate a number of Fs/N frequency clocks with different phases, wherein the number is dependent on a timing margin requirement of a multiplexor to process input data. In implementations, the low frequency clock generation and distribution circuit further including an Fs/N divider to generate an operating frequency clock associated with another input port of the input ports. In implementations, the channel local clock generation circuit further comprising an Fs/N divider to generate an operating frequency clock associated with another input port of the input ports. In implementations, the low frequency clock generation and distribution circuit further comprising a phase locked loop operating at a Fs/N frequency clock, the phase locked loop configured to generate the Fs/N frequency clock from a reference clock. In implementations, the multi-channel data processing device is a multi-channel digital-to-analog converter (DAC) and each data processing channel is a M bit DAC channel with M data paths, each data path including a set of the input ports and a multiplexor associated with each input port in the set of input ports, the channel local clock generation circuit configured to provide the different operating frequency clocks to each of the M data paths. In implementations, the channel local clock generation circuit further comprising a multi-phase clock generator configured to generate a number of Fs/N frequency clocks with different phases, wherein the number is dependent on a timing margin requirement of a multiplexor to process input data. In implementations, the system further includes a differential frequency doubler configured to generate a single-ended multiplied Fs/N frequency clock from the differential Fs/N frequency clock and convert the single-ended multiplied Fs/N frequency clock to a differential multiplied Fs/N frequency clock for use by the multiple data processing channels. In implementations, the differential frequency doubler comprises a squarer circuit implemented with one of a first transistor type or a second transistor type and a converter circuit implemented with a remaining one of a first transistor type or a second transistor type. [0006] In implementations, a method for low power clock generation, includes generating, by a phase locked loop of a multi-channel high-speed data processing device, a 1/N sampling frequency (Fs)(Fs/N) frequency clock from a reference clock, where N is larger or equal to 8, locally generating, in each high-speed data processing channel of the multi-channel high-speed data processing device, multiple operating frequency clocks for multiple multiplexors by multiplying the Fs/N frequency clock by multiple multipliers, the multiple multiplexors and the multiple multipliers in the high-speed data processing channel, controlling a multiplexor of the multiple multiplexors with an associated operating frequency clock of the multiple operating frequency clocks, and outputting data based on processing input data using the multiple operating frequency clocks and the multiple multiplexors.

[0007] In implementations, the method further includes generating, by a multi-phase clock generator in the high-speed data processing channel, multiple Fs/N frequency clocks with different phases for controlling each of the multiple multiplexors. In implementations, the different phases are 1/Fs apart. In implementations, a number of the multiple Fs/N frequency clocks is dependent on a timing margin needed by the multiple multiplexors to process the input data. In implementations, the method further includes dividing, by Fs/N divider in the multichannel high-speed data processing device, the Fs/N frequency clock to generate an operating frequency clock associated with another multiplexor of the multiple multiplexors. In implementations, the method further includes locally dividing, by Fs/N divider in the high-speed data processing channel, the Fs/N frequency clock to generate an operating frequency clock associated with another multiplexor of the multiple multiplexors. In implementations, where the Fs/N frequency clock is a differential Fs/N frequency clock and the method further includes generating, by a squarer circuit, a single-ended Fs/N frequency clock from the distributed differential Fs/N frequency clock and converting, by a converter, the single-ended Fs/N frequency clock to a differential Fs/N frequency clock for use at each data processing channel of the multi-channel data processing device.

[0008] In implementations, a method for low power clock generation includes distributing, by a low frequency clock generation and distribution circuit of a multi-channel data processing device, a 1/N sampling frequency (Fs)(Fs/N) frequency clock based on a reference clock, where N is larger or equal to 8, locally multiplying, at multiple input ports of each data processing channel of the multi-channel data processing device, the Fs/N frequency clock by a multiplier to generate an operating frequency clock associated with each input port of the multiple input ports, and generating output data by processing input data using multiple operating frequency clocks. [0009] In implementations, the method further includes generating, by a multi-phase clock generator in the data processing channel, a number of Fs/N frequency clocks with different phases. In implementations, the different phases are 1/Fs apart and the number of the Fs/N frequency clocks is dependent on a timing margin needed by a data processing channel to process the input data. In implementations, the method further includes dividing, by Fs/N divider, the Fs/N frequency clock to generate an operating frequency clock associated with another input port of the multiple input ports.

[0010] In implementations, a device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (Fs)(Fs/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential Fs/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

[0011] In implementations, the differential frequency doubler comprising a squarer circuit implemented with one of a first transistor type or a second transistor type and a converter circuit implemented with a remaining one of a first transistor type or a second transistor type. In implementations, the differential frequency doubler comprising a squarer circuit implemented with one of a n-type metal-oxide- semiconductor (NMOS) transistor or a p-type metal-oxide- semiconductor (PMOS) transistor and a converter circuit implemented with a remaining one of the NMOS transistor or the PMOS transistor. In implementations, the differential frequency doubler is integrated with a data processing channel. In implementations, the differential frequency doubler is implemented at a terminal end of the low power generation and distribution circuit to feed multiple data processing channels. In implementations, the low power generation and distribution circuit includes another differential frequency doubler configured to generate a single-ended multiplied frequency clock from a differential Fs/M frequency clock and convert the single-ended multiplied frequency clock to the differential Fs/N frequency clock, wherein M is greater than N. In implementations, the low power generation and distribution circuit further comprises a phase locked loop operating at one of the Fs/N frequency clock or the Fs/M frequency clock, the phase locked loop configured to generate the Fs/N frequency clock or the Fs/M frequency clock from a reference clock. In implementations, the differential frequency doubler is multiple differential frequency doublers.

[0012] In implementations, a method for low power clock generation and distribution includes generating, by a clock generation circuit of a data processing device, a differential 1/N sampling frequency (Fs)( Fs/N) clock, wherein N is larger or equal to 2, distributing, by a clock distribution circuit of the data processing device, the differential Fs/N frequency clock, generating, by a squarer circuit, a single-ended frequency clock from the distributed differential Fs/N frequency clock, and converting, by a converter, the single-ended frequency clock to a differential frequency clock for use at a data processing channel of the data processing device. [0013] In implementations, the method further including implementing the squarer circuit with one of a first transistor type or a second transistor type, and implementing the converter with a remaining one of a first transistor type or a second transistor type. In implementations, the method further including implementing the squarer circuit with one of a n-type metal-oxide- semiconductor (NMOS) transistor or a p-type metal-oxide- semiconductor (PMOS) transistor, and implementing the converter with a remaining one of a n-type metal-oxide- semiconductor (NMOS) transistor or a p-type metal-oxide-semiconductor (PMOS) transistor. In implementations, the method further including implementing the squarer circuit and the converter in the data processing channel. In implementations, the generating by the clock generation circuit further including generating a single-ended frequency clock from a differential Fs/M frequency clock, and converting the single-ended frequency clock based on the differential Fs/M frequency clock to the differential Fs/N frequency clock, wherein M is greater than N. In implementations, the generating by the clock generation circuit further including generating, by a phase locked loop, one of the FS/N frequency clock or the FS/M frequency clock from a reference clock.

[0014] In implementations, a method for clock generation and distribution, including generating, by a clock generation circuit of a data processing device, a 1/N sampling frequency (Fs)( Fs/N) clock, wherein N is larger or equal to 2, generating, by a squarer circuit, a single- ended frequency clock from the differential Fs/N frequency clock, distributing, by a clock distribution circuit of the data processing device, the single-ended frequency clock, and converting, by a converter, the distributed single-ended frequency clock to a differential frequency clock for use at a data processing channel of the data processing device.

[0015] In implementations, the method further including implementing the squarer circuit with one of a first transistor type or a second transistor type, and implementing the converter with a remaining one of a first transistor type or a second transistor type. In implementations, the method further including implementing the squarer circuit with one of a n-type metal-oxide- semiconductor (NMOS) transistor or a p-type metal-oxide- semiconductor (PMOS) transistor, and implementing the converter with a remaining one of a n-type metal-oxide- semiconductor (NMOS) transistor or a p-type metal-oxide-semiconductor (PMOS) transistor. In implementations, the method further including implementing the squarer circuit at the clock generation circuit, and implementing the converter at one of a terminal point of the clock distribution circuit or the data processing channel. In implementations, the generating by the clock generation circuit further including generating a single-ended frequency clock from a differential Fs/M frequency clock, and converting the single-ended frequency clock based on the differential Fs/M frequency clock to the differential Fs/N frequency clock, wherein M is greater than N. In implementations, the generating by the clock generation circuit further including generating, by a phase locked loop, one of the Fs/N frequency clock or the Fs/M frequency clock from a reference clock.

[0016] In implementations, a device includes a clock generation circuit configured to generate a 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, a squarer circuit configured to generate a single-ended frequency clock from the differential FS/N frequency clock, a clock distribution circuit configured to distribute the single-ended frequency clock, and a converter configured to convert the distributed single-ended frequency clock to a differential frequency clock for use at a data processing channel of the data processing device. [0017] In implementations, the squarer circuit comprises one of a first transistor type or a second transistor type, and the converter comprises a remaining one of a first transistor type or a second transistor type. In implementations, the squarer circuit comprises one of a n-type metal- oxide-semiconductor (NMOS) transistor or a p-type metal-oxide-semiconductor (PMOS) transistor, and the converter comprises a remaining one of a n-type metal-oxide-semiconductor (NMOS) transistor or a p-type metal-oxide-semiconductor (PMOS) transistor. In implementations, the squarer circuit is implemented at the clock generation circuit, and the converter is implemented at one of a terminal point of the clock distribution circuit or the data processing channel. In implementations, the clock generation circuit further configured to generate a single-ended frequency clock from a differential FS/M frequency clock, and convert the single-ended frequency clock based on the differential FS/M frequency clock to the differential FS/N frequency clock, wherein M is greater than N. In implementations, the clock generation circuit further comprises a phase locked loop configured to generate one of the FS/N frequency clock or the FS/M frequency clock from a reference clock.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity.

[0019] FIG. 1A is a block diagram of an example of a Fs/2 clock generation and distribution architecture for a multi-channel device.

[0020] FIG. IB is a block diagram of an example of a digital-to-analog converter (DAC) channel.

[0021] FIG. 2 is a block diagram of an example of a clock generation architecture for a multi-channel transmitter serializer.

[0022] FIG. 3 is an example of clock distribution channel loss and associated power consumption for different clock frequencies.

[0023] FIG. 4 is a block diagram of an example of a multi-channel DAC high speed device which includes a low power clock generation circuit in accordance with embodiments of this disclosure.

[0024] FIG. 5 is a block diagram of an example of a multi-channel transmitter serializer which includes a low power clock generation circuit in accordance with embodiments of this disclosure.

[0025] FIG. 6 is a diagram of multi-phase clock generation in accordance with embodiments of this disclosure.

[0026] FIG. 7 is a diagram of phase noise of a high frequency clock driving a high frequency data converter.

[0027] FIG. 8 is a block diagram of an example of a multi-channel DAC high speed device which includes a low power clock generation circuit in accordance with embodiments of this disclosure.

[0028] FIG. 9 is a flowchart of an example technique for low power clock generation for multi-channel high speed devices in accordance with embodiments of this disclosure.

[0029] FIG. 10 is a flowchart of an example technique for low power clock generation for multi-channel high speed devices in accordance with embodiments of this disclosure.

[0030] FIG. 11 is a block diagram of a phase locked loop having a high divide ratio.

[0031] FIG. 12 is a block diagram of a phase locked loop and clock multiplication with high frequency clock distribution in accordance with embodiments of this disclosure.

[0032] FIG. 13 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device in accordance with embodiments of this disclosure.

[0033] FIG. 14 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device in accordance with embodiments of this disclosure.

[0034] FIG. 15 is a block diagram of an example of a differential frequency doubler in accordance with embodiments of this disclosure.

[0035] FIG. 16 is a block diagram of an example of a differential frequency doubler circuit in accordance with embodiments of this disclosure.

[0036] FIG. 17 is a block diagram of an example of a differential frequency doubler circuit in accordance with embodiments of this disclosure.

[0037] FIG. 18 is a block diagram of an example of a low power frequency clock generation circuit in accordance with embodiments of this disclosure.

[0038] FIG. 19 is a block diagram of an example of a single-ended frequency clock generation and distribution circuit in accordance with embodiments of this disclosure.

[0039] FIG. 20 is a block diagram of an example of a single-ended frequency clock generation and distribution circuit in accordance with embodiments of this disclosure.

[0040] FIG. 21 is a block diagram of an example of a single-ended frequency clock generation and distribution circuit in accordance with embodiments of this disclosure.

[0041] FIG. 22 is a block diagram of an example of a single-ended frequency clock generation and distribution circuit in accordance with embodiments of this disclosure. [0042] FIG. 23 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device.

[0043] FIG. 24 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device.

[0044] FIG. 25 is a flowchart of an example technique for low power frequency clock generation and distribution in accordance with embodiments of this disclosure.

[0045] FIG. 26 is a flowchart of an example technique for low power frequency clock generation and distribution in accordance with embodiments of this disclosure.

DETAILED DESCRIPTION

[0046] Reference will now be made in greater detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts.

[0047] As used herein, the terminology “computer” or “computing device” includes any unit, or combination of units, capable of performing any method, or any portion or portions thereof, disclosed herein. The computer or computing device may include a processor.

[0048] As used herein, the terminology “processor” indicates one or more processors, such as one or more special purpose processors, one or more digital signal processors, one or more microprocessors, one or more controllers, one or more microcontrollers, one or more application processors, one or more central processing units (CPU)s, one or more graphics processing units (GPU)s, one or more digital signal processors (DSP)s, one or more application specific integrated circuits (ASIC)s, one or more application specific standard products, one or more field programmable gate arrays, any other type or combination of integrated circuits, one or more state machines, or any combination thereof.

[0049] As used herein, the terminology “memory” indicates any computer-usable or computer-readable medium or device that can tangibly contain, store, communicate, or transport any signal or information that may be used by or in connection with any processor. For example, a memory may be one or more read-only memories (ROM), one or more random access memories (RAM), one or more registers, low power double data rate (LPDDR) memories, one or more cache memories, one or more semiconductor memory devices, one or more magnetic media, one or more optical media, one or more magneto-optical media, or any combination thereof.

[0050] As used herein, the terminology “instructions” may include directions or expressions for performing any method, or any portion or portions thereof, disclosed herein, and may be realized in hardware, software, or any combination thereof. For example, instructions may be implemented as information, such as a computer program, stored in memory that may be executed by a processor to perform any of the respective methods, algorithms, aspects, or combinations thereof, as described herein. Instructions, or a portion thereof, may be implemented as a special purpose processor, or circuitry, that may include specialized hardware for carrying out any of the methods, algorithms, aspects, or combinations thereof, as described herein. In some implementations, portions of the instructions may be distributed across multiple processors on a single device, on multiple devices, which may communicate directly or across a network such as a local area network, a wide area network, the Internet, or a combination thereof.

[0051] As used herein, the term “application” refers generally to a unit of executable software that implements or performs one or more functions, tasks or activities. The unit of executable software generally runs in a predetermined environment and/or a processor.

[0052] As used herein, the terminology “determine" and "identify," or any variations thereof includes selecting, ascertaining, computing, looking up, receiving, determining, establishing, obtaining, or otherwise identifying or determining in any manner whatsoever using one or more of the devices and methods are shown and described herein.

[0053] As used herein, the terminology "example," "the embodiment," "implementation," "aspect," "feature," or "element" indicates serving as an example, instance, or illustration. Unless expressly indicated, any example, embodiment, implementation, aspect, feature, or element is independent of each other example, embodiment, implementation, aspect, feature, or element and may be used in combination with any other example, embodiment, implementation, aspect, feature, or element.

[0054] As used herein, the terminology "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is unless specified otherwise, or clear from context, "X includes A or B" is intended to indicate any of the natural inclusive permutations. That is if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.

[0055] Further, for simplicity of explanation, although the figures and descriptions herein may include sequences or series of steps or stages, elements of the methods disclosed herein may occur in various orders or concurrently. Additionally, elements of the methods disclosed herein may occur with other elements not explicitly presented and described herein. Furthermore, not all elements of the methods described herein may be required to implement a method in accordance with this disclosure. Although aspects, features, and elements are described herein in particular combinations, each aspect, feature, or element may be used independently or in various combinations with or without other aspects, features, and elements.

[0056] Further, the figures and descriptions provided herein may be simplified to illustrate aspects of the described embodiments that are relevant for a clear understanding of the herein disclosed processes, machines, manufactures, and/or compositions of matter, while eliminating for the purpose of clarity other aspects that may be found in typical similar devices, systems, compositions and methods. Those of ordinary skill may thus recognize that other elements and/or steps may be desirable or necessary to implement the devices, systems, compositions and methods described herein. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the disclosed embodiments, a discussion of such elements and steps may not be provided herein. However, the present disclosure is deemed to inherently include all such elements, variations, and modifications to the described aspects that would be known to those of ordinary skill in the pertinent art in light of the discussion herein.

[0057] Most high-speed, high-performance transmitter (Tx) serializers and digital-to-analog converters (DACs) require clocks at the Nyquist frequency or one half the sampling frequency (Fs/2), one half the Nyquist frequency (Fs/4), one quarter the Nyquist frequency (Fs/8), and other binary divide ratios for data interleaving or multiplexing stages, for example. Prior techniques generate the highest speed clock (Fs/2) in the clock generation block and to distribute it to the individual DAC or Serializer/Deserializer (SERDES) channels. The Fs/2 clock is used in the last multiplexing (MUX) stage and is then subsequently divided to create the synchronous Fs/4, Fs/8, Fs/16, and lower rate clocks.

[0058] FIG. 1A is a block diagram of an example of a Fs/2 clock generation and distribution architecture for a multi-channel high speed device 1000 and FIG. IB is a block diagram of an example of a digital-to-analog converter (DAC) channel 12001. The multi-channel high speed device 1000 includes a phase locked loop (PLL) 1100 which is connected to or in communication with (collectively “connected to”) multiple DAC channels 12001, 12002, . . ., 1200M. The PLL 1100 performs as a clock multiplier for a high precision external reference clock (Ref) and generates the Fs/2 clock. The Fs/2 clock can be a differential Fs/2 clock. The Fs/2 clock is distributed to each of the multiple DAC channels 12001, 12002, . . ., 1200M. A DAC channel, such as for example DAC channels 12001, includes multiple MUX stages 1210, 1220, 1230, and so on, which are driven by an appropriate division of the distributed Fs/2 clock. For example, the MUX stage 1210 is a 2:1 MUX and is directly connected to Fs/2 clock. For example, the MUX stage 1220 is a 4:2 MUX and is connected to the Fs/2 clock via a divide by 2 divider 1212 to provide a Fs/4 clock. For example, the MUX stage 1230 is an 8:4 MUX and is connected to the Fs/2 clock via the divide by 2 divider 1212 and a divide by 2 divider 1222 to provide a Fs/8 clock and so on.

[0059] FIG. 2 is a block diagram of an example of a clock generation architecture for a multi-channel transmitter serializer 2000. The multi-channel transmitter serializer 2000 includes a PLL 2100 connected to four serializer channels 23001, 23002, 2300s, and 23004 via clock distribution circuits 22001 and 22002, respectively. The PLL 2100 generates a Fs/2 clock which is distributed via the distribution circuits 22001 and 22002 and divided appropriately by dividers 2400.

[0060] As noted, the PLL 1100 and PLL 2100 generate a Fs/2 clock. This can be the done either with a PLL whose voltage-controlled oscillator (VCO) operates at a fundamental frequency of Fs/2 or at Fs/4 and multiplied up to Fs/2. Regardless of the generation technique, Fs/2 is distributed to each DAC or serializer channel, respectively. As shown in FIG. 3, clock distribution losses go up rapidly with frequency due to skin effect. To compensate for the losses, more gain stages are required. However, the gain stages are less efficient, and overall power consumption becomes prohibitive. This is especially true when the sample rates exceed 100 GHz. In this architecture, the clocking circuitry consumes the majority of the total power of the DAC or SERDES itself, while the circuitry for serializing the data is a much smaller portion. Distributing and dividing the Fs/2 clock in each channel also contributes to the high-power consumption. [0061] Another issue with this architecture concerns channel to channel synchronization. The Fs/2 clock is distributed and divided down in each separate channel. In this case, the start-up bit misalignment due to divide by two (2) phase uncertainty varies between a minimum of ±2 unit intervals (UI=l/Fs) to a maximum misalignment of ± (8UI+4UI+2UI) between each channel. This fact results in two major issues. First, the clock dividers in each channel must include additional circuitry to adjust the phase of the clocks in each channel to bring them back in to alignment with each other and this consumes more power. Secondly, a comprehensive startup calibration or training sequence is required to discover and correct for the misalignment and this requires microprocessor, which also consumes power and increases the complexity of the DAC or SERDES.

[0062] Problematically, power consumption for clock generation blocks in the DAC channels are high and cannot meet stringent system requirements. Moreover, at chip initialization, the output state of the Fs/2 clock divider is unknown. This is an issue for channel-to-channel synchronization. Jitter levels are higher as the PLL needs to increase its divide ratio to generate the Fs/2 clock. Moreover, the design of a divider running at Fs/2 is also difficult. In addition, the design of the Fs/2 clock distribution is challenging and consumes lots of power, including, but not limited to, a need for symmetrical chip layouts. This is increasingly so as the data rates goes higher.

[0063] Described herein are apparatus, devices, circuits, systems, and methods for low power clocking architecture in multi-channel high speed devices, multi-channel high speed transmitter devices, multi-channel high speed transmitter serializer devices, and the like. The methods provide low power synchronous multi-rate clocks for, but are not limited to, serializerdeserializers (SERDES), digital to analog converters (DAC), and the like. The low power clocking architecture addresses the above-mentioned issues by simplifying clock generation and distribution. In implementations, a clock rate at an input of each channel in a high-speed multichannel device is reduced to a Fs/8 frequency or lower frequency. This reduces a VCO operating frequency in the PLL and reduces the divide ratio as well.

[0064] In implementations, the low power clocking architecture uses multipliers to multiply up the Fs/8 or lower clock to higher clocks such as Fs/2, Fs/4, and the like. Consequently, unlike divider based architectures, the state of the high frequency clocks (fs/2, fs/4, and so on) can be deterministically anticipated, allowing for channel to channel synchronization or enabling channel to channel alignment. Consequently, the architecture is more robust to power supply transients and brown-outs in the field in that the alignment of the clocks would naturally return to the correct values versus the need to go through an elaborate realignment process which would result in a longer interval to recover the traffic. In implementations, in the event a divider is needed to generate a clock, the Fs/8 or lower clock is at such a low frequency that the Fs/8 or lower clock can be properly synchronized between channels using a reset signal. In implementations, any such divider is operating at the lower frequencies as opposed to Fs/2.

[0065] In implementations, the low power clocking architecture enables low power operation with localized clock generation, low frequency multi-phase clock generation, reduces the complexity and power consumption of clock distribution between PLL and each data processing channel in a multi-channel data processing device, reduces any clock feedthrough to DAC outputs, and reduces the divide ratio in PLLs which helps improve jitter performance in the PLLs.

[0066] In implementations, the stringent power requirements of pluggable digital signal processors is addressed via localized clock generation operating at low power. In implementations, inter-channel delay calibration is not needed due to the use of the multipliers. [0067] FIG. 4 is a block diagram of an example of a multi-channel DAC high speed device 4000 which includes a low power clock generation circuit 4100 in accordance with embodiments of this disclosure. The low power clock generation circuit 4100 includes a low frequency generation and distribution circuit 4110 and a channel local generation circuit 4120. The low frequency generation and distribution circuit 4110 includes a PLL 4112 which operates at and generates a low frequency clock from a reference clock (Ref). In implementations, the low frequency clock is a Fs/8 frequency clock. In implementations, the low frequency clock can be at least a Fs/8 or lower frequency clock. In implementations, the low frequency clock can be at least a differential Fs/8 or lower frequency clock. In implementations, the reference clock is a high precision external reference clock. In implementations, the reference clock can be a high frequency signal.

[0068] The multi-channel DAC high speed device 4000 includes multiple DAC channels 42001, 42002, 42003, and 42004. In implementations, the number of multiple DAC channels is M. The low frequency generation and distribution circuit 4110 generates and distributes the low frequency clock for use in the multiple DAC channels 42001, 42002, 42003, and 42004 via the channel local generation circuit 4120.

[0069] Each of the multiple DAC channels 42001, 42002, 4200s, and 42004, such as DAC channels 42001, for example, is a N bit DAC with N data paths 42101, . . ., 4210N. Each of the data paths 42101, . . ., 4210N, such as data path 42101, includes input ports 4215 associated with different operating frequency clocks. Each of the data paths 42101, . . ., 4210N, such as data path 42101, includes multiplexors 4220 such as, but not limited to, a 2:1 multiplexor 4222 operating at a Fs/2 clock frequency or rate, a 4:2 multiplexor 4224 operating at a Fs/4 clock frequency or rate, a 8:4 multiplexor 4226 operating at a Fs/8 clock frequency or rate, and a 16:8 multiplexor 4228 operating at a Fs/16 clock frequency or rate. The number of input ports 4215 along with the number and type of multiplexors comprising multiplexors 4220 associated with the input ports 4215 are illustrative and can vary without departing from the scope of the specification and claims described herein.

[0070] Each of the multiple DAC channels 42001, 42002, 42003, and 42004, such as DAC channels 42001, for example, further includes a multi-phase clock generator 4300, factoring circuits 4400, and buffers 4500. The channel local generation circuit 4120 comprises the multiphase clock generator 4300, the factoring circuits 4400, and the buffers 4500. The multi-phase clock generator 4300 operates at the low frequency clock. The multi-phase clock generator 4300 can generate multiple clocks with different phases separated by 1 UI (1/Fs) with respect to each other. The number of phases depends on the timing margin needed by the multiplexors 4220 to process the data input to the multiple DAC channels 42001, 42002, 42003, and 42004. In implementations, the multi-phase clock generator 4300 can be a delay locked loop, an injection locked oscillator, or like circuits and/or devices.

[0071] The multi-phase clock generator 4300 is connected to the 2:1 multiplexor 4222 via a quadrupler 4402 and a buffer 4502. The multi-phase clock generator 4300 is connected to the 4:2 multiplexor 4224 via a doubler 4404 and a buffer 4504. The multi-phase clock generator 4300 is connected to the 8:4 multiplexor 4226 via a buffer 4506. The multi-phase clock generator 4300 is connected to the 16:8 multiplexor 4228 via a divider 4408 and a buffer 4508. As described herein, at least some of the input ports 4215 have multipliers such as the quadrupler 4402 and the doubler 4404. In implementations, in the instance when a divider such as the divider 4408 is needed to generate the frequency clock for the multiplexor, each DAC channel is connected to a reset signal 4409, provided by a controller, to synchronize a state or state machine of the dividers on the multiple DAC channels. The divider 4408 is a low frequency divider, such as a Fs/8 divider, so that it can be synchronized between the multiple DAC channels using the reset signal shown in Fig. 4.

[0072] In the illustrative implementation of FIG. 4, the multi-phase clock generator 4300 provides 8 clocks with 1 UI phase separation, which is then processed through the appropriate factoring circuits 4400 and buffers 4500, as applicable, to generate 2 phases at the Fs/2 frequency clock for the 2:1 multiplexor 4222, to generate 4 phases at the Fs/4 frequency clock for the 4:2 multiplexor 4224, to generate 8 phases at the Fs/8 frequency clock for the 8:4 multiplexor 4226, and to generate 16 phases at the Fs/16 frequency clock for the 16:8 multiplexor 4228, which in turn are used to process the appropriate DAC input to generate the DAC output.

[0073] Consequently, the channel local generation circuit 4120 is local or in each of the multiple DAC channels 42001, 42002, 42003, and 42004 and locally generates the appropriate higher frequency clocks. That is, the channel local generation circuit 4120 receives the low frequency clock from the low frequency generation and distribution circuit 4110 and multiplies the clocks up (instead of dividing down) as and when appropriate. Therefore, the state of the higher frequency clocks (Fs/2 and Fs/4) can be deterministically anticipated and allows for channel to channel synchronization without a reset signal.

[0074] FIG. 5 is a block diagram of an example of a multi-channel transmitter serializer 5000 which includes a low power clock generation circuit 5100 in accordance with embodiments of this disclosure. The low power clock generation circuit 5100 includes a low frequency generation and distribution circuit 5110 and a channel local generation circuit 5120. The low frequency generation and distribution circuit 5110 includes a PLL 5112 which operates at and generates a low frequency clock from a reference clock and distribute via clock distribution circuits 5114 and 5116. In implementations, the low frequency clock is a Fs/8 frequency clock. In implementations, the low frequency clock can be at least a Fs/8 or lower frequency clock. In implementations, the low frequency clock can be at least a differential Fs/8 or lower frequency clock. In implementations, the reference clock is a high precision external reference clock. In implementations, the reference clock can be a high frequency signal.

[0075] The multi-channel transmitter serializer 5000 includes multiple serializer channels 52001, 52002, 52003, and 52004. In implementations, the number of multiple serializer channels is M. The low frequency generation and distribution circuit 5110 generates and distributes the low frequency clock for use in the multiple serializer channels 52001, 52002, 5200a, and 52004 via the channel local generation circuit 5120.

[0076] Each of the multiple serializer channels 52001, 52002, 5200a, and 52004, for example, serializer channel 52001 includes input ports 5210 associated with different operating frequency clocks. Each of the multiple serializer channels 52001, 52002, 5200a, and 52004, for example, serializer channel 52001 includes multipliers 5300 such as multiplier 5310 and multiplier 5320 to locally generate the frequency clocks used by the multiple serializer channels 52001, 52002, 5200a, and 52004to process the data inputs to generate the output data (output data 1 is shown as an example). The channel local generation circuit 5120 comprises the multipliers 5300. For example, the multiplier 5310 is a quadrupler which generates a Fs/2 clock frequency from the distributed Fs/8 frequency clock and the multiplier 5320 is a doubler which generates a Fs/4 clock frequency from the distributed Fs/8 frequency clock. In FIG. 5, the symbol “xl” represents a direct connection to the frequency clock being input to the multiple serializer channel. In this instance implementation, there are two xls, namely, xl 5330 and xl 5340. As described herein, at least some of the input ports 5210 have multipliers such as the double-quadrupler 8402, the multiplier 5310 and the multiplier 5320. In implementations, multi-channel transmitter serializer 5000 can include dividers 5400, such as dividers 5410 and 5420, which divide down the distributed Fs/8 frequency clock to generate a Fs/16 frequency clock. The output of the dividers 5410 and 5420 are directly connected to the serializers as shown by the xl 5330 and xl 5340 input designations. In the instance when a divider such as the dividers 5410 and 5420 are needed to generate the frequency clock for the serializer, each of the dividers 5410 and 5420 are connected to a reset signal 5500, provided by a controller, to synchronize a state or state machine of the dividers. The dividers 5410 and 5420 are low frequency dividers, such as a Fs/8 divider, so that the dividers 5410 and 5420 can be synchronized as between themselves. The dividers 5400, when appropriate, can be deemed as part of the low frequency generation and distribution circuit 5110.

[0077] Consequently, the channel local generation circuit 5120 is local or in each of the multiple serializer channels 52001, 52002, 52003, and 52004 and locally generates the appropriate high frequency clocks. That is, the channel local generation circuit 5120 receives the low frequency clock from the low frequency generation and distribution circuit 5110 and multiplies the clocks up (instead of dividing down) as and when appropriate. Therefore, the state of the frequency clocks (Fs/2, Fs/4, and Fs/8) can be deterministically anticipated and allows for channel to channel synchronization without a reset signal.

[0078] FIG. 6 is a diagram 6000 of multi-phase clock generation in accordance with embodiments of this disclosure. Shown are frequency clock outputs 6100 of a Fs/8 multi-phase generator, frequency clock outputs 6200 of a frequency doubler, and frequency clock outputs 6300 frequency quadrupler. As described herein, the 8 phases of the Fs/8 clock are each 1 UI away from each other. The 8 phases can be fed into the frequency doubler and the frequency quadrupler. The four frequency clock outputs 6200 of the frequency doubler are each 1 UI away from one another.

[0079] FIG. 7 is a diagram of phase noise plot of a high frequency clock driving a high frequency data converter such as a multiplexor of FIG. 1. The low frequency jitter is mostly dominated by the Fs/8 generated in the PLL while the high frequency jitter is dominated by the clock generation in the DAC and distribution network. Jitter contribution in both bands are important for the performance of the DAC and the clock generation scheme described herein produces low jitter clocks at the output.

[0080] FIG. 8 is a block diagram of an example of a multi-channel DAC high speed device 8000 which includes a low power clock generation circuit 8000 in accordance with embodiments of this disclosure. The low power clock generation circuit 8100 includes a low frequency generation and distribution circuit 8110 and a channel local generation circuit 8120. The low frequency generation and distribution circuit 8110 includes a PLL 8112 which operates at and generates a low frequency clock from a reference clock (Ref). In implementations, the low frequency clock is a Fs/16 frequency clock. In implementations, the low frequency clock can be at least a Fs/16 or lower frequency clock. In implementations, the low frequency clock can be at least a differential Fs/16 or lower frequency clock. In implementations, the reference clock is a high precision external reference clock. In implementations, the reference clock can be a high frequency signal.

[0081] The multi-channel DAC high speed device 8000 includes multiple DAC channels 82001, 82002, 82003, and 82004. In implementations, the number of multiple DAC channels is M. The low frequency generation and distribution circuit 8110 generates and distributes the low frequency clock for use in the multiple DAC channels 82001, 82002, 82003, and 82004 via the channel local generation circuit 8120. [0082] Each of the multiple DAC channels 82001, 82002, 8200s, and 82004, such as DAC channels 82001, for example, is a N bit DAC with N data paths 8210i , . . ., 8210N. Each of the data paths 82101, . . ., 8210N, such as data path 82101, includes input ports 8215 associated with different operating frequency clocks. Each of the data paths 8210i , . . ., 8210N, such as data path 82101, includes multiplexors 8220 such as, but not limited to, a 2:1 multiplexor 8222 operating at a Fs/2 clock frequency or rate, a 4:2 multiplexor 8224 operating at a Fs/4 clock frequency or rate, a 8:4 multiplexor 8226 operating at a Fs/8 clock frequency or rate, and a 16:8 multiplexor 8228 operating at a Fs/16 clock frequency or rate. The number of input ports 8215 along with the number and type of multiplexors comprising multiplexors 8220 associated with the input ports 8215 is illustrative and can vary without departing from the scope of the specification and claims described herein.

[0083] Each of the multiple DAC channels 82001, 82002, 82003, and 42004, such as DAC channels 82001, for example, further includes a multi-phase clock generator 8300, factoring circuits 8400, and buffers 8500. The channel local generation circuit 8120 comprises the multiphase clock generator 8300, the factoring circuits 8400, and the buffers 8500. The multi-phase clock generator 8300 operates at the low frequency clock. The multi-phase clock generator 8300 can generate multiple clocks with different phases separated by 1 UI (1/Fs) with respect to each other. The number of phases depends on the timing margin needed by the multiplexors 8220 to process the data input to the multiple DAC channels 82001, 82002, 82003, and 82004. In implementations, the multi-phase clock generator 8300 can be a delay locked loop, an injection locked oscillator, or like circuits and/or devices.

[0084] The multi-phase clock generator 8300 is connected to the 2:1 multiplexor 8222 via a double-quadrupler 8402 and a buffer 8502. The multi-phase clock generator 8300 is connected to the 4:2 multiplexor 8224 via a quadrupler 8404 and a buffer 8504. The multi-phase clock generator 8300 is connected to the 8:4 multiplexor 8226 via a doubler 8406 and a buffer 8506. The multi-phase clock generator 8300 is connected to the 16:8 multiplexor 8228 via a buffer 8508. As described herein, at least some of the input ports 8215 have multipliers such as the double-quadrupler 8402, the quadrupler 8404, and the doubler 8406.

[0085] In the illustrative implementation of FIG. 8, the multi-phase clock generator 4300 provides 16 clocks with 1 UI phase separation, which is then processed through the appropriate factoring circuits 8400 and buffers 8500, as applicable, to generate 2 phases at the Fs/2 frequency clock for the 2:1 multiplexor 8222, to generate 4 phases at the Fs/4 frequency clock for the 4:2 multiplexor 8224, to generate 8 phases at the Fs/8 frequency clock for the 8:4 multiplexor 8226, and to generate 16 phases at the Fs/16 frequency clock for the 16:8 multiplexor 8228, which in turn are used to process the appropriate DAC input to generate the DAC output.

[0086] Consequently, the channel local generation circuit 8120 is local or in each of the multiple DAC channels 82001, 82002, 82003, and 82004 and locally generates the appropriate higher frequency clocks. That is, the channel local generation circuit 4120 receives the low frequency clock from the low frequency generation and distribution circuit 4110 and multiplies the clocks up (instead of dividing down) as and when appropriate. Therefore, the state of the higher frequency clocks (Fs/2, Fs/4, and Fs/8) can be deterministically anticipated and allows for channel to channel synchronization without a reset signal.

[0087] FIG. 9 is a flowchart of an example method 9000 for low power clock generation for multi-channel high speed devices in accordance with embodiments of this disclosure. The method 9000 includes: generating 9100 a low frequency clock from a reference clock; in each high-speed data processing channel of a multi-channel high-speed data processing device, locally generating 9200 multiple clocks for multiple multiplexors by multiplying the low frequency clock by multiple multipliers; inputting 9300 a clock of the multiple clocks to an associated multiplexor of the multiple multiplexors; and outputting 9400 data based on processing input data using the multiple clocks and the multiple multiplexors. The method 9000 can be implemented by the multi-channel DAC high speed device 4000, the low power clock generation circuit 4100, the multiple DAC channels 42001, 42002, 42003, and 42004, the multi-channel transmitter serializer 5000, the low power clock generation circuit 5100, the multiple serializer channels 52001, 52002, 52003, and 52004, the multi-channel DAC high speed device 8000, the low power clock generation circuit 8100, and the multiple DAC channels 82001, 82002, 82003, and 82004, as appropriate and applicable.

[0088] The method 9000 includes generating 9100 a low frequency clock from a reference clock. A PLL is used to generate the low frequency clock from the reference clock. The low frequency clock can be a Fs/8, Fs/16, or lower frequency clock. The low frequency clock is distributed to each data processing channel of a multi-channel high-speed data processing device. In implementations, the low frequency clock can be divided down by a divider prior to reaching an associated input at the data processing channel. [0089] The method 9000 includes in each high-speed data processing channel of a multichannel high-speed data processing device, locally generating 9200 multiple frequency clocks for multiple multiplexors by multiplying the low frequency clock by multiple multipliers. Each of the high-speed data processing channels can include multiple multiplexors which operate at a multiple of the low frequency clock. Each of the high-speed data processing channels can include one or more multipliers, where a multiplier is associated with a multiplexor to multiply the low frequency clock to generate the appropriate multiplexor operating frequency clock. Each of the high-speed data processing channels can include a multi-phase clock generator which operates at the low frequency clock to generate multiple clocks with different phases separated by 1 UI (1/Fs) with respect to each other. The number of phases generated depends on the timing margin needed by the multiplexors to process the data input to the high-speed data processing channel. In implementations, each of the high-speed data processing channels can include a divider associated with a multiplexor to divide the low frequency clock to generate the appropriate multiplexor operating frequency clock. In implementations, the multi-channel highspeed data processing device can be a multi-channel DAC device, a multi-channel transmitter serializer, and the like.

[0090] The method 9000 includes inputting 9300 each frequency clock of the multiple frequency clocks to an associated multiplexor of the multiple multiplexors and outputting 9400 data based on processing input data using the multiple clocks and the multiple multiplexors. The frequency clock input to the associated multiplexor selectively controls operation of the multiplexor on the input data to generate the output data.

[0091] FIG. 10 is a flowchart of an example method 10000 for low power clock generation for multi-channel high speed devices in accordance with embodiments of this disclosure. The method 10000 includes: generating 10100 a low frequency clock from a reference clock; at multiple input ports of each data processing channel of a multi-channel data processing device, locally multiply 10200 the low frequency clock by a multiplier to generate an operating frequency clock associated with an input port; and generating 10300 output data by processing input data using multiple operating frequency clocks. The method 10000 can be implemented by the multi-channel DAC high speed device 4000, the low power clock generation circuit 4100, the multiple DAC channels 42001, 42002, 42003, and 42004, the multi-channel transmitter serializer 5000, the low power clock generation circuit 5100, the multiple serializer channels 52001, 52002, 52003, and 52004, the multi-channel DAC high speed device 8000, the low power clock generation circuit 8100, and the multiple DAC channels 82001, 82002, 8200s, and 82004, as appropriate and applicable.

[0092] The method 10000 includes generating 10100 a low frequency clock from a reference clock. A PLL is used to generate the low frequency clock from the reference clock. The low frequency clock can be a Fs/8, Fs/16, or lower frequency clock. The low frequency clock is distributed to each data processing channel of a multi-channel high-speed data processing device. [0093] The method 10000 includes at multiple input ports of each data processing channel of a multi-channel data processing device, locally multiply 10200 the low frequency clock by a multiplier to generate an operating frequency clock associated with an input port. Each data processing channel receives the low frequency clock at multiple input ports, each input port associated with circuitry operating at a defined or given operating frequency clock. For some input ports, a multiplier at the input port multiplies the low frequency clock to generate the given operating frequency clock. In implementations, the low frequency clock can be divided down by a divider prior to reaching an associated input port at the data processing channel.

[0094] The method 10000 includes generating 10300 output data by processing input data using multiple operating frequency clocks. The operating frequency clock generated at each input port is used for processing the input data to generate the output data.

[0095] A further challenge in high-speed digital to analog converter (DAC) design is the need for Fs/2 clocks for the final data interleaving or multiplexing stages. For example, an 800GHz coherent optical communications link may have a sampling rate (Fs) of the order of 120Gs/s, with the final multiplexer stage selecting alternate data streams on the rising and falling edge of a clock that is half the output sampling rate (Fs/2), or 60 GHz. A conventional technique is to use a voltage-controlled oscillator (VCO) with a center frequency of Fs/2 and build a phase- locked loop (PLL) around it. This PLL is locked to a clock reference such as a clock multiplied quartz crystal. The highest frequency that conventional low jitter reference clocks can reach is approximately 2 GHz. To clock multiply this reference to the Fs/2 center frequency requires a large divide ratio in the PLL feedback path. FIG. 11 is a block diagram of an example of a phase locked loop 11000 having a high divide ratio. As shown, a reference Fs/M clock is input into the PLL 11000 which has a large divide ratio of N=M/2. For example, M can be 64. Accordingly, the output of the PLL 11000 is a Fs/2 clock which is distributed to the DAC channels H IOOI-M. The use of a large divide ratio results in a decrease in PLL bandwidth which leads to a reduction in the suppression of the VCO noise and an increase in the jitter contribution of the charge pump (CP), frequency divider (FD), and phase frequency detector (PFD). That is, for example, the larger the divide ratio the higher the jitter performance of the PLL.

[0096] In addition, the VCO design at Fs/2 frequencies using semiconductor technology developed for low-power digital applications (~60GHz) is very difficult due to the low-quality factor (Q factor) of the inductors, capacitors, and varactors that form the resonator of the oscillator. In combination with the inherent noise generated by the switching transistors in the VCO, the Q factor of the resonator define the VCOs phase noise. The Q factor and the transistor noise increase at an ever- increasing rate as the center frequency increases. If this degradation did not occur, two VCOs at different center frequencies would have the same normalized phase noise. Since this is not the case and the normalized performance of the lower frequency VCO is superior to that of the higher frequency VCO, clock multiplication is an attractive technique to circumvent the semiconductor technologies limitations.

[0097] A frequency doubler at the output of the PLL can be used to reduce the divide ratio in a PLL and permit the use of an Fs/4 VCO. Conventional frequency doubling techniques use frequency doublers that produce a single phase of the doubled clock from two phases of the half frequency clock (clock & clockb at Fs/4). These frequency doubling techniques use a combination of p-type metal-oxide- semiconductor (PMOS) and n-type metal-oxide- semiconductor (NMOS) transistors to generate the complementary outputs. A disadvantage of creating complementary doubled clocks (a clock pair) using this technique is that the resulting clock pair have large phase and amplitude mismatch. In addition, the NMOS and PMOS devices generate differential signals that have significant asymmetry between the differential outputs over process corners. When the PMOS and NMOS devices differ in speed and/or transducer gain, the differential outputs are skewed in time with respect to each other, the amplitudes are mismatched, and the duty cycle distortion (DCD) of the outputs degrade switching performance of the final interleaving or multiplexer stage in the DAC. Since differential clocks and their character directly affect the DAC performance, circuits that only create single-ended Fs/4 outputs are of little practical use.

[0098] Described herein are apparatus, devices, circuits, systems, and methods for low power frequency clock generation and distribution. In implementations, a PLL operating at a frequency of Fs/4 or lower is connected to one or more differential frequency doublers (DFD(s)). Each DFD includes a multiplier circuit and a single-ended to differential (S2D) circuit. The multiplier circuit doubles a differential clock input to generate a doubled single-ended clock output. The S2D circuit converts the doubled single-ended clock output to a differential clock output. The DFD is a low power and low complexity frequency multiplying circuit and allows clocks to be generated at a lower frequency before doubling it. The DFD enables simplification of the PLLs, reduces the clock jitter, and produces a fully differential Fs/2 frequency clock at an output of the DFD with 50% duty cycle when the input is a differential Fs/4 frequency clock, for example. The DFDs described herein occupy a low area relative to the data processing device or a data processing channel.

[0099] In implementations, a DFD is located at a data processing channel to enable local clock generation. In implementations, a DFD is located at a distribution terminal point or end in the clock distribution circuit to service multiple data processing channels. In implementations, a DFD is located in the clock generation circuit to enable a PLL to operate at a Fs/8 or lower frequency clock. In implementations, DFDs are located in the clock generation circuit, the clock distribution circuit, or both. In implementations, a multiplier circuit and a S2D circuit can be distributed between a distribution origin point and the distribution terminal point (a “distributive DFD”). The distributive DFD enables single-ended frequency clock distribution. Reducing the frequency clock and power in clock distribution circuits is beneficial as data rates in data processing devices increase and driving long transmission-lines with 50Q termination becomes more challenging.

[0100] In implementations, the use of DFDs foregoes the need of differential in-phase and quadrature clocks as used in prior designs. The need to generate quadrature clocks makes the prior designs power consuming and limited to the frequency that the quadrature generation block can operate. Furthermore, the quadrature generation block requires startup procedures which make the test and bring-up more time consuming. The drawbacks of relying on quadrature clocks to generate double the frequency are the complexity, area, and power consumption of the quadrature generator. These issues limit the usage of these types of doublers. For example, prior devices require quadrature clocks at the input of the frequency doublers to produce balance differential outputs at twice the frequency. The DFDs herein reduce the area and power consumption by avoiding quadrature correction. The DFDs use differential clocks at the input of the doubler and produce a single-ended output running at twice the frequency. The single-ended output enters a compact single-ended to differential converter to produce the fully balanced outputs. The DFD circuits described herein are immune from common-mode noises. The DFD uses two phases (differential) inputs and produces differential outputs at twice the frequency. [0101] FIG. 12 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device 12000. In implementations, the multi-channel high speed device 12000 can be a multi-channel digital-to-analog converter (DAC), a multi-channel serializer, and the like. The multi-channel high speed device 12000 includes a frequency clock generation circuit 12100 which is connected to a frequency clock distribution circuit 12200, which in turn is connected to multiple data processing channels such as DAC channels 123001, 123002, . . ., 12300M. The frequency clock generation circuit 12100 includes a PLL 12110 which operates at and generates a frequency clock from a reference clock (Ref) and a DFD 12120 which generates a doubled frequency clock for distribution over the frequency clock distribution circuit 12200. The PLL 2110 can be a Fs/4 voltage controlled oscillator (VCO) which has a lower normalized jitter than an Fs/2 equivalent and reduces the PLL feedback divide ratio by a factor of 2. In implementations, the frequency clock is a Fs/4 frequency clock. Consequently, a divide ratio in the PLL 12110 is 16. In implementations, the frequency clock can be at least a Fs/4 or lower frequency clock. In implementations, the frequency clock can be at least a differential Fs/4 or lower frequency clock. In implementations, the reference clock is a high precision external reference clock.

[0102] Operationally, the PLL 12110 generates a differential Fs/4 frequency clock which is doubled by the DFD 12120 to output a differential Fs/2 frequency clock. The DFD 12120 multiplies the differential Fs/4 frequency clock inputs to output a single-ended Fs/2 frequency clock and then converts the single-ended Fs/2 frequency clock to a differential Fs/2 frequency clock for distribution by the frequency clock distribution circuit 12200 for use by the DAC channels 123001, 23002, . . ., 12300M. Quadrature frequency clock generation, quadrature correction, and the like are not needed.

[0103] FIG. 13 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device 13000. In implementations, the multi-channel high speed device 13000 can be a multi-channel digital-to-analog converter (DAC), a multi-channel serializer, and the like. The multi-channel high speed device 13000 includes a frequency clock generation circuit 13100 which is connected to or in communication with (collectively “connected to”) a frequency clock distribution circuit 13200, which in turn is connected to multiple data processing channels such as DAC channels 133001, 133002, . . ., 13300M. The frequency clock generation circuit 13100 includes a PLL 13110 which operates at and generates a frequency clock from a reference clock (Ref). In implementations, the frequency clock is a Fs/4 frequency clock. Consequently, a divide ratio in the PLL 13110 is 16. In implementations, the frequency clock can be at least a Fs/4 or lower frequency clock. In implementations, the frequency clock can be at least a differential Fs/4 or lower frequency clock. In implementations, the reference clock is a high precision external reference clock.

[0104] The multi-channel high speed device 13000 further includes DFDs 13400 to generate the Fs/2 frequency clocks after clock distribution, which are then used by each of the data processing channels. In implementations, the DFDs 13400 enable local or near local frequency multiplication at the DAC channels 133001, 133002, . . ., 13300M. In implementations, the frequency clock distribution circuit 13200 includes the DFDs 13400 so that multiple channels of the DAC channels 133001, 133002, . . ., 13300M can use one DFD 13400. In implementations, each of the DAC channels 133001, 133002, . . ., 13300M includes a DFD 13400.

[0105] Operationally, the PLL 13110 generates a differential Fs/4 frequency clock which is then distributed by the frequency clock distribution circuit 13200. The DFDs 13400 multiply the differential Fs/4 frequency clock inputs to output a single-ended Fs/2 frequency clock and then convert the single-ended Fs/2 frequency clock to a differential Fs/2 frequency clock for use by the DAC channels 133001, 133002, . . ., 13300M. Quadrature frequency clock generation, quadrature correction, and the like are not needed.

[0106] FIG. 14 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device 14000. In implementations, the multi-channel high speed device 14000 can be a multi-channel digital-to-analog converter (DAC), a multi-channel serializer, and the like. The multi-channel high speed device 14000 includes a frequency clock generation circuit 14100 which is connected to a frequency clock distribution circuit 14200, which in turn is connected to multiple data processing channels such as DAC channels 143001, 143002, . . ., 14300M. The frequency clock generation circuit 14100 includes a PLL 14110 which operates at and generates a frequency clock from a reference clock (Ref) and a DFD 14120 which generates a doubled frequency clock. In implementations, the frequency clock is a Fs/8 frequency clock. Consequently, a divide ratio in the PLL 14110 is 8. In implementations, the frequency clock can be at least a Fs/8 or lower frequency clock. In implementations, the frequency clock can be at least a differential Fs/8 or lower frequency clock. In implementations, the reference clock is a high precision external reference clock.

[0107] The multi-channel high speed device 14000 further includes DFDs 14400 to generate the Fs/2 frequency clocks after clock distribution, which are then used by each of the data processing channels. In implementations, the DFDs 14400 enable local or near local frequency multiplication at the DAC channels 143001, 143002, . . ., 14300M. In implementations, the frequency clock distribution circuit 14200 includes the DFDs 14400 so that multiple channels of the DAC channels 143001, 143002, . . ., 14300M can use one DFD 14400. In implementations, each of the DAC channels 143001, 143002, . . ., 14300M includes a DFD 14400.

[0108] Operationally, the PLL 14110 generates a differential Fs/8 frequency clock which is doubled by the DFD 14120 to output a differential Fs/4 frequency clock. The DFD 14120 multiplies the differential Fs/8 frequency clock inputs to output a single-ended Fs/4 frequency clock and then converts the single-ended Fs/4 frequency clock to a differential Fs/4 frequency clock for distribution by the frequency clock distribution circuit 14200. The DFDs 14400 multiply the differential Fs/4 frequency clock inputs to output a single-ended Fs/2 frequency clock and then convert the single-ended Fs/2 frequency clock to a differential Fs/2 frequency clock for use by the DAC channels 143001, 143002, . . ., 14300M. Quadrature frequency clock generation, quadrature correction, and the like are not needed.

[0109] FIG. 15 is a block diagram of an example of a DFD 15000 in accordance with embodiments of this disclosure. The DFD 15000 includes a multiplier or doubler 15100 connected to a S2D 15200. The DFD 15000 uses only differential clocks at the input of the doubler 15100 and produces a single-ended output running at twice the frequency of the differential clock inputs. The single-ended output is input to the S2D 15200 to produce the fully balanced outputs. The DFD 15000 only requires two phases (differential) inputs and produces differential outputs at twice the frequency. Consequently, the DFD 15000 does not need quadrature signals at the input.

[0110] FIG. 16 is a block diagram of an example of a DFD circuit 16000 in accordance with embodiments of this disclosure. The DFD circuit 16000 includes a squarer circuit 16100 having inputs connected to a differential clock and an output connected to an input of a S2D converter circuit 16200 and a first end of an inductor Li, which has a second end connected to VDD. The squarer circuit 16100 is a n-channel metal-oxide semiconductor (NMOS) based circuit and the S2D converter circuit 16200 is a p-channel metal-oxide semiconductor (PMOS) based circuit. [0111] The squarer circuit 16100 includes a first input NMOS transistor 16110, a second input NMOS transistor 16120, and a cascode NMOS transistor 16130. The first input NMOS transistor 16110 has a source 16112 connected to ground, a gate 16114 connected to VINP, and a drain 16116 connected to a source 16132 of the cascode NMOS transistor 16130. The second input NMOS transistor 16120 has a source 16122 connected to ground, a gate 16124 connected to VINN, and a drain 16126 connected to the source 16132 of the cascode NMOS transistor 16130. The cascode NMOS transistor 16130 has a gate 6134 connected to VCASCODE and a drain 16136 connected to the first end of the inductor Li.

[0112] The S2D converter circuit 16200 includes a capacitor C, a bias resistor RBIAS, a first output PMOS transistor 16210, a second output PMOS transistor 16220, and an inductor L2. The first end of the inductor Li is connected to a first end of the capacitor C and to a source 16212 of the first output PMOS transistor 16210. The first output PMOS transistor 16210 has a gate 16214 connected to VBIAS and a drain 16216 connected to a first end of the inductor L2. The bias resistor RBIAS is connected to a second end of the capacitor C and to a gate 16224 of the second output PMOS transistor 16220. The second output PMOS transistor 16220 has a source 16222 connected to VDD and a drain 16226 connected to a second end of the inductor L2. The inductor L2 is tuned to a squared frequency by being tapped at a midpoint to ground. A differential output, VOP and VON, is obtained from the drain 16216 and the drain 16226, respectively.

[0113] FIG. 17 is a block diagram of an example of a DFD circuit 17000 in accordance with embodiments of this disclosure. The DFD circuit 17000 includes a squarer circuit 17100 having inputs connected to a differential clock and an output connected to an input of a S2D converter circuit 17200 and a first end of an inductor Li, which has a second end connected to ground. The squarer circuit 17100 is a PMOS based circuit and the S2D converter circuit 17200 is a NMOS based circuit.

[0114] The squarer circuit 17100 includes a first input PMOS transistor 17110, a second input PMOS transistor 17120, and a cascode PMOS transistor 17130. The first input PMOS transistor 17110 has a source 17112 connected to VDD, a gate 17114 connected to VINP, and a drain 17116 connected to a source 17132 of the cascode PMOS transistor 17130. The second input PMOS transistor 17120 has a source 17122 connected to VDD, a gate 17124 connected to VINN, and a drain 17126 connected to the source 17132 of the cascode PMOS transistor 17130. The cascode PMOS transistor 17130 has a gate 17134 connected to VCASCODE and a drain 17136 connected to the first end of the inductor Li.

[0115] The S2D converter circuit 17200 includes a capacitor C, a bias resistor RBIAS, a first output NMOS transistor 17210, a second output NMOS transistor 17220, and an inductor L2. The first end of the inductor Li is connected to a first end of the capacitor C and to a source 17212 of the first output NMOS transistor 17210. The first output NMOS transistor 17210 has a gate 17214 connected to VBIAS and a drain 17216 connected to a first end of the inductor L2. The bias resistor RBIAS is connected to a second end of the capacitor C and to a gate 17224 of the second output NMOS transistor 17220. The second output NMOS transistor 17220 has a source 17222 connected to ground and a drain 17226 connected to a second end of the inductor L2. The inductor L2 is tuned to a squared frequency by being tapped at a midpoint to ground. A differential output, VOP and VON, is obtained from the drain 17216 and the drain 17226, respectively.

[0116] Referring now to both FIG. 16 and FIG. 17, differential clocks at the input enter the squarer circuit 16100 (17100) and the single-ended output of the squarer circuit 16100 (17100) is folded back into the S2D converter circuit 16200 (17200) to generate the differential output. The single-ended output is immune from any common-mode noises. Prior art current frequency doublers do not provide differential outputs based on differential inputs and require quadrature inputs to generate differential outputs. The requirement of quadrature inputs necessitates the use of mixed NMOS and PMOS transistors to generate the complementary signals comprising the quadrature inputs. As noted herein, each of the squarer circuit 16100, the S2D converter circuit 16200, the squarer circuit 17100, and the S2D converter circuit 17200 use either NMOS or PMOS transistors. Consequently, the differential output is not sensitive to PMOS/NMOS matching.

[0117] In both of the circuits of FIG. 16 and FIG. 17, the generated two differential phases at the output (squarer or doubler outputs) move together over process comers and are not sensitive to the process variation of NMOS and PMOS. In implementations, the circuits of FIG. 16 and FIG. 17 are insensitive to FS (NMOS=fast, PMOS=slow) and SF (NMOS=slow, PMOS=fast). In these conditions the output of the NMOS -based circuits will be faster/slower compared to the output of the PMOS-based output. The drawback of relying on both (mixed) NMOS and PMOS devices to generate differential signals is that it creates significant asymmetry between the differential outputs over process corners. When the PMOS and NMOS devices differ in speed and/or transducer gain, the differential outputs are skewed in time with respect to each other, the amplitudes are mismatched and, the duty cycle distortion (DCD) of the outputs degrade switching performance of a final interleaving multiplexor stage in the DAC.

[0118] FIG. 18 is a block diagram of an example of a low power frequency generation circuit 18000 in accordance with embodiments of this disclosure. In implementations, the DFD described herein enables use of PLLs at a low frequency and subsequent low frequency distribution. The low power frequency generation circuit 18000 includes multiple DFDs 18100, 18200, and 18300 which enable a PLL to operate at and generate a differential Fs/X frequency clock. The DFD 18100 processes the differential Fs/X frequency clock to generate a differential 2*Fs/X frequency clock as described herein. The DFD 18200 processes the differential 2*Fs/X frequency clock to generate a differential 4*Fs/X frequency clock as described herein. The DFD 18300 processes the differential 4*Fs/X frequency clock to generate a differential 8*Fs/X frequency clock as described herein. In implementations, one or more of the DFDs 18100, 18200, and 18300 can be located and connected as part of a clock generation circuit, as part of a clock distribution circuit, or combinations thereof as described herein. In implementations, any of the differential clock frequencies can be distributed to data processing channels. In implementations, the differential 2*Fs/X clock frequency is distributed to data processing channels. In implementations, the differential 4*Fs/X clock frequency is distributed to data processing channels. The number of DFDs is illustrative and any number of DFDs can be used without departing from the scope of the specification and claims.

[0119] FIG. 19 is a block diagram of an example of a single-ended clock generation and distribution circuit 19000 in accordance with embodiments of this disclosure. The single-ended clock generation and distribution circuit 19000 includes a PLL 19100 connected to a distributed or distributive DFD 19200. The distributed or distributive DFD 19200 includes a single-ended clock distribution circuit 19210 and a S2D 19220. The single-ended clock distribution circuit 19210 includes a multiplier 19212 and a transmission line 19214. The S2D 19220 can provide impedance matching for the transmission line 19214.

[0120] A frequency clock is generated at the PLL, which is then multiplied by the multiplier 19212 to generate a single-ended frequency clock. The single-ended frequency clock is distributed or transmitted via the transmission line 19214 from the multiplier 19212 to the S2D 19220 at a transmission line termination. The S2D 19220 converts the single-ended frequency clock to a differential frequency clock. The multiplier 19212 and the S2D 19220 of the distributed or distributive DFD 19200 operate as described herein. The single-ended clock generation and distribution circuit 19000 can reduce clock distribution power consumption. [0121] FIG. 20 is a block diagram of an example of a single-ended clock generation and distribution circuit 20000 in accordance with embodiments of this disclosure. The single-ended clock generation and distribution circuit 20000 includes a multiplier 20100, a transmission line 20200, and a S2D 20300. The single-ended clock generation and distribution circuit 20000 functions and operates as described herein.

[0122] A Fs/4 frequency clock is generated by a PLL, which is then multiplied by the multiplier 20100 to generate a single-ended Fs/2 frequency clock. The single-ended Fs/2 frequency clock is distributed or transmitted via the transmission line 20200 from the multiplier 20100 to the S2D 20300 at a transmission line termination. The S2D 20300 converts the single- ended Fs/2 frequency clock to a differential Fs/2 frequency clock, which is then distributed for use by data processing channels.

[0123] FIG. 21 is a block diagram of an example of a single-ended clock generation and distribution circuit 21000 in accordance with embodiments of this disclosure. The single-ended clock generation and distribution circuit 21000 includes a multiplier 21100, a transmission line 21200, and a S2D 21300. The single-ended clock generation and distribution circuit 21000 functions and operates as described herein.

[0124] A Fs/8 frequency clock is generated by a PLL, which is then multiplied by the multiplier 21100 to generate a single-ended Fs/4 frequency clock. The single-ended Fs/4 frequency clock is distributed or transmitted via the transmission line 21200 from the multiplier 21100 to the S2D 21300 at a transmission line termination. The S2D 21300 converts the single- ended Fs/4 frequency clock to a differential Fs/4 frequency clock, which is then distributed for use by data processing channels.

[0125] FIG. 22 is a block diagram of an example of a single-ended clock generation and distribution circuit 22000 in accordance with embodiments of this disclosure. The single-ended clock generation and distribution circuit 22000 includes a multiplier 22100, a transmission line 22200, and a S2D 22300. The single-ended clock generation and distribution circuit 22000 functions and operates as described herein.

[0126] A Fs/16 frequency clock is generated by a PLL, which is then multiplied by the multiplier 22100 to generate a single-ended Fs/8 frequency clock. The single-ended Fs/8 frequency clock is distributed or transmitted via the transmission line 22200 from the multiplier 22100 to the S2D 22300 at a transmission line termination. The S2D 22300 converts the single- ended Fs/8 frequency clock to a differential Fs/8 frequency clock, which is then distributed for use by data processing channels.

[0127] FIG. 23 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device 23000. In implementations, the multi-channel high speed device 23000 can be a multi-channel digital-to-analog converter (DAC), a multi-channel serializer, and the like. The multi-channel high speed device 23000 includes a frequency clock generation circuit 23100 which is connected to a clock distribution circuit 23200, which in turn is connected to multiple data processing channels such as DAC channels 233001, 233002, . . ., 23300M. The frequency clock generation circuit 23100 includes a PLL 23110 which operates at and generates a frequency clock from a reference clock (Ref) and a multiplier 23120 which generates a doubled frequency clock. In implementations, the clock distribution circuit 23200 includes S2Ds 23400 at or near distribution end point. In implementations, multiples of the DAC channels 233001, 233002, . . ., 23300M are connected to one of the S2Ds 23400. In implementations, each of the DAC channels 233001, 233002, . . ., 23300M can include a S2D 23400. In implementations, the multiplier 23120 and the S2Ds 23400 constitute a distributed DFD as described herein. In implementations, the frequency clock is a Fs/4 frequency clock. Consequently, a divide ratio in the PLL 23110 is 16. In implementations, the reference clock is a high precision external reference clock.

[0128] Operationally, the PLL 23110 generates a differential Fs/4 frequency clock which is doubled by the multiplier 23120 to output a single-ended Fs/2 frequency clock for distribution by the clock distribution circuit 23200. The S2Ds 23400 convert the single-ended Fs/2 frequency clock to a differential Fs/2 frequency clock for use by the DAC channels 233001, 233002, . . ., 23300M.

[0129] FIG. 24 is a block diagram of an example of a frequency clock generation and distribution architecture for a multi-channel high speed device. In implementations, the multi- channel high speed device 24000 can be a multi-channel digital-to-analog converter (DAC), a multi-channel serializer, and the like. The multi-channel high speed device 24000 includes a frequency clock generation circuit 24100 which is connected to a frequency clock distribution circuit 24200, which in turn is connected to multiple data processing channels such as DAC channels 243001, 243002, . . ., 24300M. The frequency clock generation circuit 24100 includes a PLL 24110 which operates at and generates a frequency clock from a reference clock (Ref) and a multiplier 24120 which generates a doubled frequency clock. In implementations, the frequency clock distribution circuit 24200 includes S2Ds 24400 at or near the distribution end point and DFDs 24500 at or near the distribution end point. In implementations, multiples of the DAC channels 243001, 243002, . . ., 24300M are connected to one of the DFDs 24500. In implementations, each of the DAC channels 243001, 243002, . . ., 24300M can include a S2D 24400 and a DFD 24500. In implementations, the multiplier 24120, the S2Ds 24400, and the DFDs 24500 constitute a distributed DFD as described herein. In implementations, the frequency clock is a Fs/8 frequency clock. Consequently, a divide ratio in the PLL 24110 is 8, which can improve performance of the PLL. In implementations, the reference clock is a high precision external reference clock.

[0130] Operationally, the PLL 24110 generates a differential Fs/8 frequency clock which is doubled by the multiplier 24120 to output a single-ended Fs/4 frequency clock for distribution by the frequency clock distribution circuit 24200. The S2Ds 24400 convert the single-ended Fs/4 frequency clock to a differential Fs/4 frequency clock and the DFDs 24500 convert the differential Fs/4 frequency clock to a differential Fs/2 frequency clock for use by the DAC channels 243001, 243002, . . ., 24300M.

[0131] FIG. 25 is a flowchart of an example method 25000 for low power frequency clock generation and distribution in accordance with embodiments of this disclosure. The method includes: generating 25100 a frequency clock from a reference clock; distributing 25200 the frequency clock; generating 25300 a single-ended multiplied frequency clock from the distributed frequency clock; and converting 25400 the single-ended multiplied frequency clock to a differential multiplied frequency clock for use at a data processing channel. The method 25000 can be implemented by the multi-channel high speed device 13000, the frequency clock generation circuit 13100, the frequency clock distribution circuit 13200, the multiple DAC channels 133001, 133002, . . ., 13300M, the multi-channel high speed device 14000, the frequency clock generation circuit 14100, the frequency clock distribution circuit 14200, the DAC channels 143001, 143002, • • ., 14300M, the DFD 25000, the DFD circuit 16000, the DFD circuit 17000, the low power frequency generation circuit 18000, the single-ended clock generation and distribution circuit 19000, the single-ended clock generation and distribution circuit 20000, the single-ended clock generation and distribution circuit 21000, the single-ended clock generation and distribution circuit 22000, the multi-channel high speed device 23000, the frequency clock generation circuit 23100, the clock distribution circuit 23200, the DAC channels 233001, 233002, . . ., 23300M, the multi-channel high speed device 24000, the frequency clock generation circuit 24100, the frequency clock distribution circuit 24200, and the DAC channels 243001, 243002, . . ., 24300M, as appropriate and applicable.

[0132] The method 25000 includes generating 25100 a frequency clock from a reference clock. A PLL generates a frequency clock from a reference clock. The frequency clock can be a Fs/4, Fs/8, Fs/16, or lower frequency clock. In implementations, generating can include differential frequency doubling the frequency clock from the PLL.

[0133] The method 25000 includes distributing 25200 the frequency clock. The output of the PLL is distributed toward the data processing channels. In implementations, the output of a DFD is distributed toward the data processing channels.

[0134] The method 25000 includes generating 25300 a single-ended multiplied frequency clock from the distributed frequency clock. The distributed frequency clock is processed through a multiplier which generates the single-ended multiplied frequency clock.

[0135] The method 25000 includes converting 25400 the single-ended multiplied frequency clock to a differential multiplied frequency clock for use at a data processing channel. The single-ended multiplied frequency clock is processed through a converter which generates the differential multiplied frequency clock. The differential multiplied frequency clock can be used by the data processing channels.

[0136] FIG. 26 is a flowchart of an example method 26000 for low power frequency clock generation and distribution in accordance with embodiments of this disclosure. The method includes: generating 26100 a frequency clock from a reference clock; generating 26200 a single- ended multiplied frequency clock from the frequency clock; distributing 26300 the single-ended multiplied frequency clock; and converting 26400 the single-ended multiplied frequency clock to a differential multiplied frequency clock for use at a data processing channel. The method 26000 can be implemented by the multi-channel high speed device 13000, the frequency clock generation circuit 13100, the frequency clock distribution circuit 13200, the multiple DAC channels 133001, 133002, . . ., 13300M, the multi-channel high speed device 14000, the frequency clock generation circuit 14100, the frequency clock distribution circuit 14200, the DAC channels 143001, 143002, • • ., 14300M, the DFD 15000, the DFD circuit 16000, the DFD circuit 17000, the low power frequency generation circuit 18000, the single-ended clock generation and distribution circuit 19000, the single-ended clock generation and distribution circuit 20000, the single-ended clock generation and distribution circuit 21000, the single-ended clock generation and distribution circuit 22000, the multi-channel high speed device 23000, the frequency clock generation circuit 23100, the clock distribution circuit 23200, the DAC channels 233001, 233002, . . ., 23300M, the multi-channel high speed device 24000, the frequency clock generation circuit 24100, the frequency clock distribution circuit 24200, and the DAC channels 243001, 243002, . . ., 24300M, as appropriate and applicable.

[0137] The method 26000 includes generating 26100 a frequency clock from a reference clock. A PLL generates a frequency clock from a reference clock. The frequency clock can be a Fs/4, Fs/8, Fs/16, or lower frequency clock.

[0138] The method 26000 includes generating 26200 a single-ended multiplied frequency clock from the frequency clock. The frequency clock is processed through a multiplier which generates the single-ended multiplied frequency clock.

[0139] The method 26000 includes distributing 26300 the single-ended multiplied frequency clock. The output of the multiplier is distributed toward the data processing channels.

[0140] The method 26000 includes converting 26400 the single-ended multiplied frequency clock to a differential multiplied frequency clock for use at a data processing channel. The single-ended multiplied frequency clock is processed through a converter which generates the differential multiplied frequency clock. The differential multiplied frequency clock can be used by the data processing channels.

[0141] Although some embodiments herein refer to methods, it will be appreciated by one skilled in the art that they may also be embodied as a system or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "processor," "device," or "system." Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more the computer readable mediums having the computer readable program code embodied thereon. Any combination of one or more computer readable mediums may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0142] A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0143] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to CDs, DVDs, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0144] Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0145] Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. [0146] These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

[0147] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

[0148] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures.

[0149] While the disclosure has been described in connection with certain embodiments, it is to be understood that the disclosure is not to be limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications, combinations, and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.