CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a PCT International Application, which claims benefit of U.S. Application Serial No. 17/584,543, filed on January 26, 2022, the contents of which is incorporated by reference herein in its entirety.

STATEMENT OF FEDERALLY FUNDED RESEARCH

[0002] None.

TECHNICAL FIELD OF INVENTION

[0003] The present invention relates to creating a three-dimensional capacitor structure in a photosensitive in-glass ceramic substrate, in particular, creating capacitors and in conjunction with other passive components for filters, surge protectors and storage for electronic, microwave and radio frequencies.

BACKGROUND OF THE INVENTION

[0004] Photosensitive glass structures have been suggested for a number of micromachining and microfabrication processes such as integrated electronic elements in conjunction with other elements systems or subsystems. Silicon microfabrication of traditional glass is expensive and low yield while injection modeling or embossing processes produce inconsistent shapes. Silicon microfabrication processes rely on expensive capital equipment; photolithography and reactive ion etching or ion beam milling tools that generally cost in excess of one million dollars each and require an ultra-clean, high-production silicon fabrication facility costing millions to billions more. Injection molding and embossing are less costly methods of producing three-dimensional shapes but generate defects within the transfer or have differences due to the stochastic curing process.

[0005] This invention creates a cost-effective glass ceramic three-dimensional capacitor structure or three-dimensional capacitor array device. Where a glass ceramic substrate has demonstrated capability to form such structures through the processing of both the vertical as well as horizontal planes either separately or at the same time to form two or three-dimensional Capacitive devices. SUMMARY OF THE INVENTION

[0006] The present invention includes a method to fabricate a substrate with one or more, two or three dimensional capacitor devices by preparing a photosensitive glass substrate with via or post and further coating or filling with one or more conductive layers typically a metal, dielectric material and a top layer conductive layer typically a metal.

[0007] A method of fabrication and device made by preparing a photosensitive glass ceramic composite substrate including at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout including one or more, two or three-dimensional capacitor device in the photosensitive glass substrate, exposing at least one portion of the photosensitive glass substrate to an activating energy source, exposing the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature, cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass-crystalline substrate and etching the glass-crystalline substrate with an etchant solution to form one or more angled channels or through holes that are then used in the creation of capacitive device.

[0008] The present invention provides a glass ceramics capacitive device including: a first glass-crystalline substrate including one or more electrical conduction paths in the glasscrystalline substrate, and a metal coating applied to the one or more electrical conduction paths, wherein the first glass-crystalline substrate includes at least silica, lithium oxide, aluminum oxide, and cerium oxide; a second glass-crystalline substrate including: one or more second electrical conduction paths in the second glass-crystalline substrate; and a second metal coating applied to the one or more second electrical conduction paths, wherein the second glass-crystalline substrate includes at least silica, lithium oxide, aluminum oxide, and cerium oxide; a layer of dielectric material positioned between the first glass-crystalline substrate and the second glass-crystalline substrate; and one or more via, posts, channels, or a combination thereof connecting the first glass-crystalline substrate and the second glass-crystalline substrate. The first termination may be connected to the first glass-crystalline substrate and the second termination may be connected to the second glass-crystalline substrate. The glass ceramic capacitive device may perform as a voltage storage device. The metal coating, the second metal coating or both may be Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, or mixtures and alloys thereof. The dielectric layer may be Ta2Os, AI2O3, or other vapor phase dielectrics including but not limited to AI2O3. [0009] The present invention provides a method of making a capacitive device created in or on photosensitive glass ceramics including the steps of: providing a photosensitive glass ceramic substrate including at least silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout on the photosensitive glass ceramic substrate, wherein the design layout includes one or more structures to form one or more electrical conduction paths; exposing at least one portion of the photosensitive glass ceramic substrate to an activating energy source; heating the photosensitive glass ceramic substrate to a heating phase of at least ten minutes above its glass transition temperature; cooling the photosensitive glass cerami c substrate to transform at least part of the exposed glass to a crystalline material to form a glasscrystalline substrate; etching the glass-crystalline substrate with an etchant solution to form the one or more three dimensional etched structure in the glass-crystalline substrate; optionally converting a portion of the glass-crystalline substrate adjacent to the three dimensional etched structure to a ceramic phase; rinsing the glass-crystalline substrate with a dilute glass etchant to form a high surface area texture to glass area; coating the via or post channels with a first metal to form a bottom electrode; coating at least a portion of the structure with a dielectric media; coating the via or post channels with a second metal to form a top electrode; removing at least a portion of the top and dielectric media to provide electrical contact or free standing device; and connecting the first metal, the second metal or both to a circuitry through a surface or buried contact.

[0010] The coating of the first metal, the second metal or both uses atomic layer deposition (ALD). The glass ceramics capacitive device preforms as a voltage storage. The first metal, the second metal or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3 or mixtures and alloys thereof. The dielectric layer may be Ta2Os, AI2O3 or other vapor phase dielectrics.

[0011] In one embodiment, the present invention includes a method of making a capacitive device within one or more three-dimensional structures etched within a single photosensitive glass ceramic substrate, including: providing a photosensitive glass ceramic substrate including silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout on the photosensitive glass ceramic substrate, wherein the design layout includes one or more structures to form one or more three-dimensional structures; exposing at least one portion of the photosensitive glass ceramic substrate to an activating energy source; heating the photosensitive glass ceramic substrate for at least ten minutes to a temperature above its glass transition temperature; cooling the photosensitive glass ceramic substrate to transform at least part of the exposed photosensitive glass ceramic substrate to a crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate with an etchant solution to form the one or more three-dimensional etched structures in the glass-crystalline substrate, wherein the etched glass-crystalline substrate and an unexposed portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1; rinsing an interior surface of each of the one or more three dimensional etched structures with a dilute glass etchant to increase the surface area of the interior surface to increase a capacitance of the glass ceramic capacitive device; coating at least a portion of the interior surface of each of the one or more three dimensional etched structures with a first metal to form a bottom electrode; coating at least a portion of the bottom electrode with a dielectric media; coating at least a portion of the dielectric media with a second metal to form a top electrode; and removing at least a portion of the top electrode and the dielectric media to provide an electrical contact configured to make an electrical connection between the capacitive device and a circuitry. In one aspect, the method further includes converting a portion of the glass-crystalline substrate adjacent to the one or more three dimensional etched structures to a ceramic phase. In another aspect, the coating with the first metal, the coating with the second metal, or both are performed with atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another aspect, the dielectric layer includes Ta2Os, AI2O3 or another vapor-phase dielectric, or a combination thereof.

[0012] In another embodiment, the present invention includes a capacitive device including: a photosensitive glass ceramic substrate including silica, lithium oxide, aluminum oxide, and cerium oxide; a glass-crystalline substrate; and one or more three-dimensional structures etched in the glass-crystalline substrate, wherein the glass-crystalline substrate and a non-glasscrystalline portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1, each three-dimensional structure including an interior surface with a high-surface-area texture; a first metal coating disposed on at least a portion the interior surface of each three- dimensional structure as a bottom electrode; a dielectric coating disposed on a least a portion of the bottom electrode; a second metal coating disposed on at least a portion of the dielectric coating as a top electrode; and one or more surface contacts or one or more buried contacts in electrical communication with the bottom electrode or the top electrode and configured to be connected to a circuitry. In one aspect, the device further includes a ceramic phase adjacent to the one or more three dimensional etched structures. In another aspect, the coating with the first metal, the coating with the second metal, or both are disposed with atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another aspect, the dielectric layer includes Ta2Os, AI2O3, another vaporphase dielectric, or a combination thereof.

[0013] In another embodiment, the present invention includes a capacitive device including a single photosensitive glass ceramic substrate including: silica, lithium oxide, aluminum oxide, and cerium oxide; a first glass-crystalline substrate; a second glass-crystalline substrate; a three-dimensional structure etched in the first glass-crystalline substrate and the second glasscrystalline substrate, wherein the first and second glass-crystalline substrates and a non-glass- crystalline portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30: 1; a first metal coating disposed on the first glass-crystalline substrate; a second metal coating disposed on the second glass-crystalline substrate; a layer of dielectric material disposed between the first glass-crystalline substrate and the second glass-crystalline substrate; and one or more vias, one or more post channels, or a combination thereof directly connecting the first glass-crystalline substrate and the second glass-crystalline substrate, wherein the one or more vias or one or more post channels are formed having a high-surface area texture that provides an increased capacitance in the capacitive device. In one aspect, the capacitive device further includes a ceramic phase adjacent to the three-dimensional structure. In another aspect, the first metal coating, the second metal coating, or both are disposed with atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another aspect, the dielectric material includes Ta2Os, AI2O3, another vaporphase dielectric, or a combination thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Further benefits and advantages of the present invention will become more apparent from the following description of various embodiments that are given by way of example with reference to the accompanying drawings:

[0015] FIGURE 1 Show a through hole via with 65um diameter, 72um center-to-center pitch.

[0016] FIGURE 2 Blind via in a 1mm thick substrate where the via depth is 440pm and the top diameter is 41 m and bottom diameter is 19pm. [0017] FIGURES 3A-3B show the top view of high surface area and high aspect ratio devices in/on APEX® Glass.

[0018] FIGURE 4 Side view of filled through hole via in/on APEX® Glass.

[0019] FIGURES 5A-5B Show an exploded view of a blind via with the ADL capacitor structure.

DESCRIPTION OF THE INVENTION

[0020] While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention.

[0021] To facilitate the understanding of this invention, a number of terms are defined below. Terms defined herein have meanings as commonly understood by a person of ordinary skill in the areas relevant to the present invention. Terms such as “a”, “an” and “the” are not intended to refer to only a singular entity, but include the general class of which a specific example may be used for illustration. The terminology herein is used to describe specific embodiments of the invention, but their usage does not delimit the invention, except as outlined in the claims.

[0022] To address these needs, the present inventors developed a glass ceramic (APEX®) Glass ceramic) as a novel packaging and substrate material for semiconductors, RF electronics, microwave electronics, and optical imaging. APEX® Glass ceramic is processed using first generation semiconductor equipment in a simple three step process and the final material can be fashioned into either glass, ceramic, or contain regions of both glass and ceramic. The APEX® Glass ceramic possesses several benefits over current materials, including: easily fabricated high density via, demonstrated microfluidic capability, micro-lens or micro-lens array, high Young’s modulus for stiffer packages, halogen free manufacturing, and economical manufacturing. Photoetchable glasses have several advantages for the fabrication of a wide variety of microsystems components. Microstructures have been produced relatively inexpensively with these glasses using conventional semiconductor processing equipment. In general, glasses have high temperature stability, good mechanical and electrical properties, and have better chemical resistance than plastics and many metals. To our knowledge, the only commercially available photoetchable glass is FOTURAN®, made by Schott Corporation and imported into the U.S. only by Invenios Inc. FOTURAN® comprises a lithium-aluminum- silicate glass containing traces of silver ions plus other trace elements specifically silicon oxide (SiCh) of 75-85% by weight, lithium oxide (Li2O) of 7-11% by weight, aluminum oxide (A12O1) of 3-6% by weight, sodium oxide (Na2O) of 1-2% by weight, 0.2-0.5% by weight antimonium trioxide (Sb2O3) or arsenic oxide (As2O3), silver oxide (Ag2O) of 0.05-0.15% by weight, and cerium oxide (CeCh) of 0.01- 0.04% by weight. As used herein the terms “APEX® Glass ceramic”, “APEX® glass” or simply “APEX®” is used to denote one embodiment of the glass ceramic composition of the present invention.

[0023] When exposed to UV -light within the absorption band of cerium oxide the cerium oxide acts as sensitizers, absorbing a photon and losing an electron that reduces neighboring silver oxide to form silver atoms, e.g.,

3+ + 4+ 0

Ce + Ag = Ce + Ag

[0024] The silver atoms coalesce into silver nanoclusters during the baking process and induce nucleation sites for crystallization of the surrounding glass. If exposed to UV light through a mask, only the exposed regions of the glass will crystallize during subsequent heat treatment.

[0025] This heat treatment must be performed at a temperature near the glass transformation temperature (e.g., greater than 465°C. in air for FOTURAN®). The crystalline phase is more soluble in etchants, such as hydrofluoric acid (HF), than the unexposed vitreous, amorphous regions. In particular, the crystalline regions of FOTURAN® are etched about 20 times faster than the amorphous regions in 10% HF, enabling microstructures with wall slopes ratios of about 20: 1 when the exposed regions are removed.

[0026] Generally, glass ceramics materials have had limited success in microstructure formation plagued by performance, uniformity, usability by others and availability issues. Past glass-ceramic materials have yield etch aspect-ratio of approximately 15:1, in contrast APEX® Glass has an average etch aspect ratio greater than 50:1. This allows users to create smaller and deeper features. Additionally, our manufacturing process enables product yields of greater than 90% (legacy glass yields are closer to 50%). Lastly, in legacy glass ceramics, approximately only 30% of the glass is converted into the ceramic state, whereas with APEX™ Glass ceramic this conversion is closer to 70%.

[0027] APEX® Glass composition provides three main mechanisms for its enhanced performance: (1) The higher amount of silver leads to the formation of smaller ceramic crystals which are etched faster at the grain boundaries, (2) the decrease in silica content (the main constituent etched by the HF acid) decreases the undesired etching of unexposed material, and (3) the higher total weight percent of the alkali metals and boron oxide produces a much more homogeneous glass during manufacturing.

[0028] Ceramicization of the glass is accomplished by exposing the entire glass substrate to approximately 20J/cm ² of 310nm light. When trying to create glass spaces within the ceramic, users expose all of the material, except where the glass is to remain glass. In one embodiment, the present invention provides a quartz/chrome mask containing a variety of concentric circles with different diameters.

[0029] The present invention includes a method for fabricating an inductive device in or on glass ceramic structure electrical microwave and radio frequency applications. The glass ceramic substrate may be a photosensitive glass substrate having a wide number of compositional variations including but not limited to: 60 - 76 weight % silica; at least 3 weight % K2O with 6 weight % - 16 weight % of a combination of K2O and Na2O; 0.003-1 weight % of at least one oxide selected from the group consisting of Ag2O and A112O: 0.003-2 weight % CU2O; 0.75 weight % - 7 weight % B2O3, and 6 - 7 weight % AI2O3; with the combination of B2O3; and AI2O3 not exceeding 13 weight %; 8-15 weight % Li2O; and 0.001 - 0.1 weight % CeCh. This and other varied compositions are generally referred to as the APEX® glass.

[0030] The exposed portion may be transformed into a crystalline material by heating the glass substrate to a temperature near the glass transformation temperature. When etching the glass substrate in an etchant such as hydrofluoric acid, the anisotropic-etch ratio of the exposed portion to the unexposed portion is at least 30:1 when the glass is exposed to a broad spectrum mid-ultraviolet (about 308-312 nm) flood lamp to provide a shaped glass structure that has an aspect ratio of at least 30:1, and to create an inductive structure. The mask for the exposure can be of a halftone mask that provides a continuous grey scale to the exposure to form a curved structure for the creation of an inductive structure/device. A digital mask can also be used with the flood exposure and can be used to produce the creation of an inductive structure/device. The exposed glass is then baked, typically in a two-step process. Temperature range heated between of 420°C-520°C for between 10 minutes to 2 hours, for the coalescing of silver ions into silver nanoparticles and temperature range heated between 520°C-620°C for between 10 minutes and 2 hours allowing the lithium oxide to form around the silver nanoparticles. The glass plate is then etched. The glass substrate is etched in an etchant, of HF solution, typically 5% to 10% by volume, wherein the etch ratio of the exposed portion to that of the unexposed portion is at least 30:1 when exposed with a broad spectrum mid-ultraviolet flood light, and greater than 30:1 when exposed with a laser, to provide a shaped glass structure with an anisotropic-etch ratio of at least 30:1.

[0031] The present invention includes one or more inductive structures created in the multiple via or posts of a glass-ceramic substrate, such a process employing the photodefinable glass structure containing at least one or more, two or three-dimensional capacitor devices. The capacitive device is formed by one via or a series of vias, where the via is either through a hole or blind via, a depositing a bottom electrode, dielectric, and top electrode using an atomic layer deposition (ALD) process. The via may also receive an additional low-concentration rinse, with an etchant, such as dilute HF. The dilute HF will pattern or texture the ceramic wall of the via. The texturing of the ceramic wall significantly increases to the surface area of the structure directly increasing the capacitance of the device.

[0032] The capacitive device consists of a conductive layer that adheres well to glass, a dielectric layer, a top conductive layer and a final barrier layer. The APEX® Glass dimensional structure is coated with a layer less than 2 microns of TiN or other electrode material, followed by a 2 micron or less dielectric layer of Ta2Os, AI2O3 or other vapor phase dielectrics including but not limited to AI2O3. AI2O3 at 380 °C using TMA and O3 - cycle time: 3.5 s. The AI2O3 layer is then heated in oxygen ambient to 300°C for 5 min fully oxidized the dielectric layer. Then depositing a top electrode of less than 2 microns of TiN by ALD. The top and bottom electrode need to be constructed from the same material to prevent the formation of a space charge in the dielectric. Depending on the size of the work function difference the space charge may be greater than what can be overcome with an external voltage without breaking down the dielectric layer rendering the capacitor useless. Eliminating the work function issue can be achieved by creating an ohmic contact between the electrodes and dielectric. Additional metal and insulator layers may be added to increase the capacitance.

[0033] Preferred Embodiment. A preferred structure is to create a capacitor structure where the via or post has a dilute HF wash to create a high textured surface area coated TiW metallization for the bottom electrode, Tantalum pent oxide for the dielectric and TiW metallization for the top electrode. The TiW bottom electrode requires a two-step ADL process. Step one is to deposit Ti using TiCh rate of 1.67A/cycle in about 1.8 s cycle time at a substrate temperature of 300°C to 400°C. The second step is to deposit tungsten (W) using Si-H and W-F mixed on the substrate’s surface prior to purging. A linear growth rate of W requires equal portions of each reactant during the ALD cycle. Typical ALD growth for Tungsten is 6A cycle, with a cycle time of 3.5s with a substrate temperature between 177°C to 325°C. Alternating the ALD cycle from W to Ti at the substrate temperature necessary to achieve the deposition of both metals will result in the formation of a TiW layer. The process is repeated until the TiW structure reaches 20A. Next a Ta2Os is formed by ALD using TaCh precursor in the presence of atomic hydrogen. Tantalum films are deposited at a substrate temperature of 25-400°C with an ALD cycle time of 1.8 s. After each ALD cycle, the Tantalum films are exposed to O2 for 30 seconds while the substrate is at 400°C. This converts the metallic Tantalum film to Ta2Os. The device is completed by applying a top electrode of TiW in the same manner as the bottom electrode. The very nature of ALD process enables dense conformal coatings.

[0034] Finishing the capacitor structure requires etching down to the bottom electrode so electrical connection can be made to both contacts of the capacitor. This is accomplished by coating the structure with a standard positive photoresist. Exposing the photoresist with a rectangular over part of the capacitor structure. Then developing and removing the photoresist over the capacitor exposing the top TiW photoresist electrode. The TiW electrode is etched with SFe/He plasmas using a Tegal 804 plasma etching system. This etch rate with 200W of forward power is 200A/min. This etch is preferentially relative to the Ta2Os layer, making the Ta2C>5 layer an effective etch stop. The Ta2Os plasma etch using Ar/Cl (10%/90%) mixture with 300W of forward power with a 1200A/min etch rate. The Ar/Cl plasma does not attack/etch the TiW bottom electrode. This allows the top and bottom electrodes for the capacitor to be connected to the rest of the circuit by a wide number of standard thick and thin film processes.

[0035] A second embodiment uses a through hole via that may have the ceramic phase etched with a dilute HF solution to create a textured high surface area on one side or both sides to partially or fully remove the glass-ceramic as the base substrate for the capacitive structure. A third embodiment uses a post on one or both sides of the APEX® Glass substrate that may have the ceramic phase etched with a dilute HF to create to a high surface area capacitive structure.

[0036] In one embodiment, the present invention includes a method of making a capacitive device within one or more three-dimensional structures etched within a single photosensitive glass ceramic substrate, comprising, consisting essentially of, or consisting of: providing a photosensitive glass ceramic substrate including silica, lithium oxide, aluminum oxide, and cerium oxide; masking a design layout on the photosensitive glass ceramic substrate, wherein the design layout includes one or more structures to form one or more three-dimensional structures; exposing at least one portion of the photosensitive glass ceramic substrate to an activating energy source; heating the photosensitive glass ceramic substrate for at least ten minutes to a temperature above its glass transition temperature; cooling the photosensitive glass ceramic substrate to transform at least part of the exposed photosensitive glass ceramic substrate to a crystalline material to form a glass-crystalline substrate; etching the glasscrystalline substrate with an etchant solution to form the one or more three-dimensional etched structures in the glass-crystalline substrate, wherein the etched glass-crystalline substrate and an unexposed portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1; rinsing an interior surface of each of the one or more three dimensional etched structures with a dilute glass etchant to increase the surface area of the interior surface to increase a capacitance of the glass ceramic capacitive device; coating at least a portion of the interior surface of each of the one or more three dimensional etched structures with a first metal to form a bottom electrode; coating at least a portion of the bottom electrode with a dielectric media; coating at least a portion of the dielectric media with a second metal to form a top electrode; and removing at least a portion of the top electrode and the dielectric media to provide an electrical contact configured to make an electrical connection between the capacitive device and a circuitry. In one aspect, the method further includes converting a portion of the glass-crystalline substrate adjacent to the one or more three dimensional etched structures to a ceramic phase. In another aspect, the coating with the first metal, the coating with the second metal, or both is performed with atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another aspect, the dielectric layer includes Ta2Os, AI2O3 or another vapor-phase dielectric, or a combination thereof.

[0037] In another embodiment, the present invention includes a capacitive device comprising, consisting essentially of, or consisting of: a photosensitive glass ceramic substrate including silica, lithium oxide, aluminum oxide, and cerium oxide; a glass-crystalline substrate; and one or more three-dimensional structures etched in the glass-crystalline substrate, wherein the glass-crystalline substrate and a non-glass-crystalline portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30:1, each three-dimensional structure including an interior surface with a high-surface-area texture; a first metal coating disposed on at least a portion the interior surface of each three-dimensional structure as a bottom electrode; a dielectric coating disposed on a least a portion of the bottom electrode; a second metal coating disposed on at least a portion of the dielectric coating as a top electrode; and one or more surface contacts or one or more buried contacts in electrical communication with the bottom electrode or the top electrode and configured to be connected to a circuitry. In one aspect, the device further includes a ceramic phase adjacent to the one or more three dimensional etched structures. In another aspect, the coating with the first metal, the coating with the second metal, or both is disposed with atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another aspect, the dielectric layer includes Ta2Os, AI2O3, another vapor-phase dielectric, or a combination thereof.

[0038] In another embodiment, the present invention includes a capacitive device including a single photosensitive glass ceramic substrate comprising, consisting essentially of, or consisting of: silica, lithium oxide, aluminum oxide, and cerium oxide; a first glass-crystalline substrate; a second glass-crystalline substrate; a three-dimensional structure etched in the first glass-crystalline substrate and the second glass-crystalline substrate, wherein the first and second glass-crystalline substrates and a non-glass-crystalline portion of the photosensitive glass substrate have an anisotropic etch ratio of at least 30: 1; a first metal coating disposed on the first glass-crystalline substrate; a second metal coating disposed on the second glasscrystalline substrate; a layer of dielectric material disposed between the first glass-crystalline substrate and the second glass-crystalline substrate; and one or more vias, one or more post channels, or a combination thereof directly connecting the first glass-crystalline substrate and the second glass-crystalline substrate, wherein the one or more vias or one or more post channels are formed having a high-surface area texture that provides an increased capacitance in the capacitive device. In one aspect, the capacitive device further includes a ceramic phase adjacent to the three-dimensional structure. In another aspect, the first metal coating, the second metal coating, or both are disposed with atomic layer deposition (ALD). In another aspect, the first metal, the second metal, or both include Au, Ag, Pt, Cu, W, TiW, TiN, TaN, WN, AI2O3, a mixture of two or more thereof, or an alloy of two or more thereof. In another aspect, the dielectric material includes Ta2Os, AI2O3, another vapor-phase dielectric, or a combination thereof. [0039] It will be understood that particular embodiments described herein are shown by way of illustration and not as limitations of the invention. The principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain, using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of this invention and are covered by the claims.

[0040] All publications and patent applications mentioned in the specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

[0041] The use of the word “a” or “an” when used in conjunction with the term “comprising” in the claims and/or the specification may mean “one,” but it is also consistent with the meaning of “one or more,” “at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and/or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

[0042] As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “includes” and “include”) or “containing” (and any form of containing, such as “contains” and “contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In embodiments of any of the compositions and methods provided herein, “comprising” may be replaced with “consisting essentially of’ or “consisting of.” As used herein, the phrase “consisting essentially of’ requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention. As used herein, the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method/process step, or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), property(ies), method/process step(s), or limitation(s)) only.

[0043] As used herein, the term “or combinations thereof’ refers to all permutations and combinations of the listed items preceding the term. For example, “A, B, C, or combinations thereof’ is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of one or more item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.

[0044] As used herein, words of approximation such as, without limitation, “about,” “substantial,” or “substantially,” refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present. The extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skill in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature. In general, but subject to the preceding discussion, a numerical value herein that is modified by a word of approximation such as “about” may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.

[0045] All of the devices and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the devices and/or methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skill in the art are deemed to be within the spirit, scope, and concept of the invention as defined by the appended claims.

[0046] Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosure. Accordingly, the protection sought herein is as set forth in the claims below. [0047] Modifications, additions, or omissions may be made to the systems and apparatuses described herein without departing from the scope of the invention. The components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses may be performed by more, fewer, or other components. The methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order.

[0048] To aid the Patent Office, and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims to invoke paragraph 6 of 35 U.S.C. § 112 as it exists on the date of filing hereof unless the words “means for” or “step for” are explicitly used in the particular claim.

[0049] For each of the claims, each dependent claim can depend both from the independent claim and from each of the prior dependent claims for each and every claim so long as the prior claim provides a proper antecedent basis for a claim term or element.