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WO/2020/010399A1 |
A method of determining the optical delay of an optical waveguide, the method including the steps of: transmitting a first periodic modulated optical signal along the optical waveguide with a first modulation frequency; determining a pha...
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WO/2020/009735A1 |
In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enab...
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WO/2020/007374A1 |
A distributed continuous vibration monitoring system, comprising a plurality of sub-systems respectively disposed at various measurement points of an ultra-high-rise building. Each of the sub-system comprise: a terminal, comprising a mem...
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WO/2020/004075A1 |
This technology relates to a reception device and a reception method which make it possible to shorten the time that elapses before transmission control information is acquired. Provided is a reception device equipped with a control unit...
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WO/2020/000079A1 |
A clock recovery device recovers frequency and timing information from an incoming packet stream over asynchronous packet networks. A phase locked loop (PLL) block has predefined states and includes a type II PLL. One of the states invol...
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WO/2020/004050A1 |
The present technique relates to a reception device and a reception method enabling a reduction in jitters when a stream is processed. Provided is a reception device comprising a control unit that controls, when divided variable-length p...
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WO/2020/001365A1 |
Provided by embodiments of the present application are an adjustment method for a PHY in a FlexE group, related equipment and a storage medium, which are used for flexible adjustment of a PHY in a FlexE group in working state. A receivin...
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WO/2019/243565A1 |
Method for processing a sequence of digital signal samples comprising a first sub-sequence and a second sub-sequence, said method comprising: forming (106) a first block of samples comprising the first sub-sequence and a second block of ...
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WO/2019/241080A1 |
Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality o...
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WO/2019/240853A1 |
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signa...
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WO/2019/236781A1 |
A receiver module (110) includes a clock recovery circuit (116) and a decision feedback equalizer (DFE) circuit (112). The DFE circuit (112) includes a data feedback loop (130) configured to sample an input data stream combined with equa...
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WO/2019/235101A1 |
The present invention is characterized in that a computer executes the following: a time-of-generation estimation process in which, when data from a device is received, the time-of-generation of the data is estimated using the reception ...
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WO/2019/235568A1 |
This frame synchronization device (10) is equipped with: a multiplication unit (11) which, for each of a plurality of symbols of a received signal, multiplies the received signal by the inverse complex number of a prescribed synchronizat...
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WO/2019/231771A1 |
According to one embodiment, a phase locked loop (PLL) circuit includes a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency and a second VCO to generate a second signal having a second frequenc...
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WO/2019/232073A1 |
Disclosed methods of terrestrial station monitoring of downlink signal quality include receiving a sequence of samples of reference symbol slots of a downlink burst, and estimating a time offset between a local clock and a timing of a sy...
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WO/2019/067194A9 |
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data...
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WO/2019/213891A1 |
The present application discloses a method and a device for a wireless communication node. The method comprises: a first node determining whether the first node is within a coverage area; sending Q wireless signals of a second type, the ...
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WO/2019/212629A1 |
Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, wher...
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WO/2019/212630A1 |
Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line inter...
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WO/2019/205670A1 |
Disclosed in embodiments of the present application are a phase detection method, a phase detection circuit, and a clock recovery device. The method comprises: receiving a first signal, and performing a (2M-1) level decision on the first...
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WO/2019/205925A1 |
Provided are a communication method and apparatus. The communication method comprises: a terminal device determining a first detection method, wherein the first detection method is determined according to a first message, or the first de...
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WO/2019/209409A1 |
Methods, apparatus, and systems for monitoring and measuring signal characteristics for signals received over a multi-wire, multi-phase interface are disclosed. Signals present on each line of a 3-line communication interface are sampled...
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WO/2019/204535A1 |
A multi-radio access technology circuit is provided. The multi-RAT circuit includes a radio frequency circuit coupled to an interconnect medium. The RF circuit includes a power head circuit configured to receive a local oscillation pilot...
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WO/2019/203396A1 |
A CRUM apparatus includes a power extraction circuit that extracts power from a high value of a clock signal received from an image forming apparatus, and a control circuit activated by the power extracted by the power extraction circuit...
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WO/2019/197480A1 |
The invention relates to a synchronization device (26i) designed to be inserted into a reception channel of a multichannel radio signal reception system between an interfacing module (10i) and a digital signal processing module (12i), th...
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WO/2019/197420A1 |
A radio receiver device(1), arranged to receive a radio signal (38) modulated with a plurality of data symbols, comprises an analogue-to-digital converter (32) that is clocked by a first clock signal (54) and is arranged to receive the r...
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WO/2019/199609A1 |
The disclosed embodiments provide a system that implements a low-aperture-delay sampler. The system includes a sampler input, which receives an input signal, and a clock input, which receives a clock signal. The system also includes: a f...
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WO/2019/192322A1 |
Provided are a communication method and a communication apparatus. The method comprises: a terminal device receiving time information via a first channel, wherein the first channel is a broadcast channel and/or a control channel, or a br...
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WO/2019/195687A1 |
Apparatuses, systems, and methods for performing timing synchronization between a base station and a user equipment device within an unlicensed spectrum band. In some scenarios, beamforming tracking may also be performed. Upon determinin...
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WO/2019/194066A1 |
In the present invention, differential input pins INP/INN are connected to a differential transmission path. A receiver circuit 602 receives a differential input signal input to the differential input pins INP/INN. A latch circuit 604 la...
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WO/2019/191969A1 |
Embodiments of the present application provide a communication method and apparatus. The communication method comprises: a terminal device sends a first indication message, the first indication message being used for indicating the first...
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WO/2019/192300A1 |
Embodiments of the present application provide a clock phase recovery apparatus and method, and a chip. The apparatus comprises an ADC, a chromatic dispersion compensation unit, a digital interpolator, an MIMO balance unit, and a clock o...
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WO/2019/191455A1 |
Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase e...
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WO/2019/186443A1 |
This disclosure relates to methods and systems for providing contemporaneous audio streaming from a host Bluetooth device (201) to a plurality of receiving Bluetooth devices (202). In an embodiment, a method (400) may include disabling a...
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WO/2019/129760A9 |
The present invention relates to an adaptive synchronization device for demodulating a signal in linear modulation (x). The device functions from a sampled version of the signal (x). The device being characterized in that it comprises: -...
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WO/2019/173875A1 |
Apparatus and methods are presented for synchronising a slave device signal to a reference timebase, in situations where the slave device lacks knowledge of the propagation delay for signals from the reference device, e.g. if the positio...
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WO/2019/176619A1 |
[Problem] To enhance the quality of time information by suppressing time skipping that occurs during switching of transmission paths in a BC apparatus in which transmission paths for time information of at least two systems are connected...
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WO/2019/174554A1 |
The present application provides a time delay compensation method and device. The device determines a first time delay value of a first data stream from a first physical port of the device to a second physical port of the device and a se...
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WO/2019/177503A1 |
A method and a first device (110A) for synchronizing a first clock in the first device (110A) with a second clock in a second device (110B). The first device (110A) estimates 5 (A430) a relative clock phase offset, based on a sequence of...
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WO/2019/177945A1 |
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler (202) configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data ...
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WO/2019/176660A1 |
[Problem] To provide a time synchronization system, a management device, a time synchronization method, and a program with which it is possible to filter GPS jamming that causes micro-disturbances to continue. [Solution] A management dev...
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WO/2019/175898A1 |
According to the embodiment discloses a method providing direct RF sampling of the received signal in a full duplex system. A sampler in the full-duplex system comprises a buffer to clip an amplitude information from each of a coupled tr...
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WO/2019/171669A1 |
This switch device comprises: a relay unit for carrying out first relay processing for relaying data between function units mounted in a vehicle and belonging to different VLANs; a calculation unit for calculating time correction informa...
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WO/2019/173039A1 |
A software-defined network controller (SDN controller) defines a first network flow to be selectively implemented by a networking device according to a first network operation profile. The SDN controller defines a second network flow to ...
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WO/2019/167415A1 |
The present invention is provided with: one or more transmission/reception means for transmitting and receiving a synchronization packet containing time information by being connected to a network constituting a communication channel for...
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WO/2019/166771A1 |
Control apparatus to control operation of a data buffer to which data items are written according to a write pointer which advances in position in response to an input data item rate and from which data items are read according to a read...
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WO/2019/167361A1 |
The purpose of the present invention is to shorten the duration of a possible abnormal operation of a phase synchronization unit of an optical signal reception device in the event of a fault, and to reduce fluctuation in the frequency of...
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WO/2019/165954A1 |
A data bit width conversion method and device, and a computer-readable storage medium. The method comprises: generating, according to parallel data conversion information, control information of data bit width conversion; and performing,...
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WO/2019/165370A1 |
A wireless device may receive packets according to a protocol, such as Bluetooth, and may rapidly react to receive an interfering RF packet instead of dropping the first RF packet and the interfering RF packet, to decrease message delay ...
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WO/2019/163443A1 |
A communication system according to one example of the present disclosure is a communication system in which a plurality of communication devices are connected to a network. The plurality of communication devices include: a time master w...
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