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WO/2022/204632A1 |
A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage ...
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WO/2022/198894A1 |
Embodiments of the present application provide a signal generation circuit and a memory. The signal generation circuit comprises: a clock delay module, configured to delay an initial pulse signal to output an intermediate signal, wherein...
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WO/2022/188353A1 |
The embodiments of the present application provide a pulse generation circuit and a staggered pulse generation circuit. The pulse generation circuit comprises: an oscillation module, which is used for receiving a control signal, and gene...
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WO/2022/191904A1 |
An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may f...
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WO/2022/187643A1 |
A ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last ...
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WO/2022/187498A1 |
A square wave oscillator includes a Schmitt Trigger (101) with a first output that outputs a first output current, a capacitor (103) connected to the first output of the Schmitt Trigger (101), and a resistor (105) that connects the capac...
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WO/2022/187226A1 |
A system and method for differentiating between different modes of pulsed electrical discharges via of an amplitude to time (ATC) conversion circuit is described. A bipolar ATC circuit is used to add together the positive and negative po...
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WO/2022/187529A1 |
A current-mode Schmitt Trigger (200) includes a plurality of current output stages (201A-C) connected to a common supply voltage that powers the current-mode Schmitt Trigger, a main input on one of the current output stages (201a) that r...
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WO/2022/179309A1 |
Disclosed in the present application are a clock management apparatus, a clock frequency division module and a system-on-a-chip. The clock management apparatus comprises a clock synchronization signal generator, a plurality of clock gate...
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WO/2022/171429A1 |
An implantable pulse generator (1) comprises a pulse generation device (12) configured to generate an output pulse, the pulse generation device (12) comprising a control unit (120), a shock generation circuitry (121) and an output circui...
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WO/2022/164633A1 |
A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch include...
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WO/2022/155888A1 |
An RC relaxation oscillator, comprising: a voltage generating circuit (50), a capacitor charging and discharging circuit (60), a voltage comparison circuit (70), and a logic control circuit (80). The voltage generating circuit (50) compr...
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WO/2022/155176A1 |
In some examples, a circuit includes a clock divider (102) and a calibration circuit (104) coupled to the clock divider. The clock divider includes digital-to-time converter (DTC) (204). The calibration circuit configured to determine a ...
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WO/2022/152051A1 |
The present disclosure relates to a processor and a computing system. Provided is a processor, comprising: a pipeline stage, which comprises a time sequence device; and a first clock driving circuit, which is used for providing a clock s...
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WO/2022/150188A1 |
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does no...
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WO/2022/133988A1 |
A multi-phase clock generation circuit, used for generating multi-phase non-overlapping clock signals. The multi-phase clock generation circuit comprises a loop structure formed by the input ends and output ends of a plurality of logic g...
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WO/2022/135024A1 |
A pulse signal output circuit (50) and a flowmeter (11). The pulse signal output circuit (50) comprises a signal receiving module (21), a photoelectric coupler (22), and a signal conversion module (23). The signal receiving module (21) i...
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WO/2022/139890A1 |
A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, secon...
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WO/2022/140071A1 |
A pulsed power circuit (30, 31, 32) including an inductor (55) having a hybrid core of a switch magnetic material arranged and selected to function as a magnetic switch a damping magnetic material arranged and selected to damp energy ref...
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WO/2022/139659A1 |
The present invention describes a high voltage pulse generator unit comprising a primary side, a transformer and a secondary side, wherein the primary side comprises a winding and wherein the secondary side comprises multiple windings an...
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WO/2022/129048A1 |
An oscillator circuit arrangement comprises a switched capacitor circuit (100) comprising at least one capacitor (110) selectively coupled to one of a supply terminal (103) and a terminal (10) for ground potential. A chopper circuit (400...
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WO/2022/131924A1 |
A method of generating pulses for controlling an optical device is described comprising: receiving a clock signal and one or more logical pulse selection signals (314), wherein the timing quality of the clock signal, preferably the timin...
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WO/2022/125309A1 |
The present disclosure includes storage circuits, such latches. In one embodiment, a circuit includes a plurality of latches, each latch including a first N-type transistor formed in a first P-type material, a first P-type transistor for...
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WO/2022/122854A1 |
A method of generating an output signal based on a single flux quantum (SFQ) pulse includes receiving the SFQ pulse and splitting it into a first path and a second path. The split SFQ pulse of the second path is stored in a latch. A seco...
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WO/2022/121365A1 |
The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, which comprises: an input terminal, which is used for receiving input data; an output termin...
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WO/2022/118389A1 |
A sonic wave generator (10) is configured to generate ultrasonic waves of a predetermined frequency for driving away harmful animals. The sonic wave generator (10) is provided with a power source (11), a switch (12), an oscillation circu...
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WO/2022/116416A1 |
Provided in the present application is a Schmitt trigger, comprising a first inverter which forms a series connection between an input node and a connection node, a second inverter which forms a series connection between the connection n...
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WO/2022/113341A1 |
This voltage-controlled oscillator is configured comprising: a ring oscillator (3) in which a plurality of inverters (4-n) that invert the signal level of an inputted signal and output the signal after the signal level is inverted are co...
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WO/2022/110963A1 |
A rapid mechanical switch (17) test system and method of a high-voltage direct-current circuit breaker. The system comprises: a plurality of rapid mechanical switches (17) to be tested which are connected in series, at least one position...
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WO/2022/114446A1 |
The present invention relates to a multi-wave generation system for generating waveforms used in various fields such as functional surface processing machines, waveform generation devices, or research fields using waveforms. To this end,...
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WO/2022/115650A1 |
A circuit and method are described for generating a low-jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing th...
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WO/2022/107670A1 |
A semiconductor circuit according to one aspect of the present disclosure comprises a non-volatile latch circuit which stores k-bit data and m-bit error correction data for the k-bit data.
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WO/2022/108072A1 |
The present invention relates to a high voltage pulse generator and a pasteurization system using same and, more particularly, to an ultrasonic humidifier and a driving method thereof, wherein: a pasteurization system is applied to an ul...
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WO/2022/101407A1 |
Disclosed herein are systems and techniques for microphone array calibration, as well as communication systems in which calibrated microphones can be used. The systems and techniques disclosed herein may provide both phase and magnitude ...
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WO/2022/095160A1 |
An adaptive random spiking neuron implementation method based on a ferroelectric field-effect transistor, belonging to the technical field of spiking neurons in neuromorphic computing. Hardware in the method comprises a ferroelectric fie...
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WO/2022/094440A1 |
An apparatus (120) includes a differential input pair (123), a first resistor, a second resistor, and a comparator. The differential input pair (123) having a first differential input (125) and a second differential input (126). The firs...
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WO/2022/090171A1 |
There is provided an aerosol generation device (100) comprising a power system (600) and a controller (102). The power system comprises a first supercapacitor module (604) and a second supercapacitor module (606). The controller is confi...
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WO/2022/091744A1 |
A combined logic circuit according to one aspect of the present disclosure is provided with: a latch circuit configured using a Single Phase Clocking circuit including a NAND circuit; and an inverter circuit which inverts the output sign...
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WO/2022/080624A1 |
The present invention relates to an adaptive soft-start and soft-stop device for a converter and, more specifically, provides an adaptive soft-start and soft-stop device for a converter, wherein an input voltage (Vin) and an output volta...
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WO/2022/081596A1 |
Embodiments herein may relate to a processor core and a hardware accelerator coupled to the processor core. The hardware accelerator may include five latches, wherein respective latches are clocked by respective clocks. In some embodimen...
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WO/2022/081165A1 |
Various examples are provided for disposable medical sensors that can be used for the detection of cerebral spinal fluid. In one example, a medical sensing system includes a disposable sensing unit comprising a functionalized sensing are...
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WO/2022/081321A1 |
An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a...
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WO/2022/080677A1 |
The present invention relates to a low-power control apparatus using a sleep timer, and more particularly, to a low-power control apparatus using a sleep timer, which, in order to minimize power consumption according to a load degree of ...
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WO/2022/075150A1 |
[Problem] To suppress variations of a signal line voltage. [Solution] A signal line driving circuit for driving a plurality of signal lines, comprising: a reference voltage generating unit for generating, in a first period before the plu...
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WO/2022/076099A1 |
A TMR flip-flop (300) includes a set of master-gate-latch circuits (320, 340) including a first set of inputs to receive a first digital signal (D), and a second set of inputs to receive a clock (CLK); and a voting circuit (330) includin...
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WO/2022/075492A1 |
A fuel ionization apparatus according to the present invention comprises: a first electrode unit and a second electrode unit provided in a fuel supply pipe through which fuel flows; and a pulse generation unit for applying electricity (p...
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WO/2022/072947A1 |
A pulse generator is disclosed. The pulse generator includes a DC source; a plurality of switches, a transformer; and a pulsing output. The pulse generator can be coupled with a plasma chamber. The pulsing output outputs high voltage pul...
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WO/2022/062711A1 |
The present disclosure provides a digital fingerprint generator and a digital fingerprint generation method. The digital fingerprint generator comprises: a control circuit, generating a control word; a first pulse generation circuit, con...
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WO/2022/059400A1 |
An oscillator circuit (10) is provided with a plurality of oscillators (11) and wires (12) that connect the plurality of oscillators (11). The wires (12) are disposed so as to form a closed circuit that passes once through each of the pl...
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WO/2022/059068A1 |
A comparator circuit (5) outputs digital signals (XQP, XQN) corresponding to differential signals (IN, /IN) to a flip-flop (3) having a prescribed prohibition input. A conversion circuit (4) differentially amplifies the differential sign...
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