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WO/2006/104802A1 |
The present invention relates to stored value cards (233, 234) and improved bank processing systems (222, 224, 241). In particular, it relates to systems and methods that load value into demand deposit (243) and plastic account number ac...
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WO/2006/099846A1 |
The invention relates to a method and to a signal processing unit for processing the signal of a plurality of analog input signals (4.1) by means of a common analog-digital converter (4.0) which detects, in a consecutive manner and in on...
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WO/2006/099147A1 |
Self-timed interfaces and methods are provided for interfacing different timing domains. These self-timed interfaces receive a strobe signal from a component operating under a first clock domain. A first signal path of the self-timed int...
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WO/2006/085273A1 |
A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the regi...
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WO/2006/069438A1 |
A method of accommodating legacy devices in which application memory is not able to operate fast enough to reliably receive data from a relay or other external device is disclosed. An application queue memory space is provided, either as...
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WO/2006/063395A1 |
A method for feature reduction in a training set for a learning machine such as a Support Vector Machine (SVM). In one embodiment the method includes a step (35) of receiving input training data vectors xi of a training set. The input tr...
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WO/2006/064962A1 |
Methods and apparatus provide for transferring data to and from one or more processors of a multi-processor system over a first bus at a first frequency; transferring data to and from one or more interface circuits over a second bus at a...
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WO/2006/062142A1 |
It is possible to increase the compression ratio of the encoding method using a dictionary such as LZ77, LZ78, LZW for sample strings of the audio signal and video signal. Each sample is aligned at the MSB side (73), divided from the MSB...
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WO/2006/055282A2 |
A multiprocessor system (206) having a plurality of processors (304-306), each processor capable of processing at least one queue (404A-404N) of at least one service application, and at least one task (402A-402N) comprising at least one ...
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WO/2006/043274A2 |
Web content based on markup language technology is delivered to a client device running a browser or similar application through a markup language file manipulator. Files requested by a client device are processed through the markup lang...
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WO/2006/041165A1 |
There are provided a method for encoding signals by separating them by using a common multiplier so as to improve the compression efficiency of an audio signal and a method for obtaining a multiplier common to a numeric set including an ...
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WO/2006/037677A1 |
The invention relates to a method for reading out sensor data from an intermediate memory (110), written by at least one sensor (10) in the intermediate memory at a data rate (Tpas). According to the invention, a sampling rate (Tsg) is s...
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WO/2006/024781A1 |
The invention concerns a method for managing a buffer memory used for a computer programme using a MMU memory management unit. The invention is characterized in that it comprises a step which consists in detecting an access exceeding the...
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WO/2006/007801A1 |
The present invention provides a First-in-first-out memory to improve the empty-full indicator generating logic unit of the existing FIFO such that the First-in-first-out memory can generate a state adjusting signal which is output direc...
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WO/2006/004165A1 |
A mask which is used for divided recording that completes an image with a plurality of scanning operations by using a plurality of different colors of ink, and which can prevent the occurrence of grains in the middle of recording and red...
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WO/2005/122689A2 |
The present invention is directed to a method and system for securing a device (e.g. a security token). The method comprising the steps of: providing physical actuation mechanism (e.g. a switch) to the device; disabling some function(s) ...
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WO/2005/116815A1 |
Methods and apparatus provide for efficient message passing communication between subsystems. In one aspect of the present invention FIFOs (202, 203, 204, 212, 216) are disposed between the subsystems (102, 104, 110) to buffer the messag...
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WO/2005/112269A1 |
Audio information is encoded, sample by sample, by creating a table of encoded audio sample values in which redundant ones of the encoded audio sample values share common table entries. The encoding method may include comparing a current...
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WO/2005/088889A1 |
A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually asynchronous, and are coupled by the synchronization module. The synchroniz...
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WO/2005/085990A1 |
Systems and techniques are disclosed relating to shifting a plurality of input data bits to the left or right by a number of bit positions as a function of a binary value of a plurality of shift control bits. A first shifter element may ...
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WO/2005/078572A1 |
A FIFO memory device (300) comprises a storage device (321) which is a non-volatile FIFO comprising a plurality of non-volatile storage elements or latches. The FIFO memory device (300) also comprises an input stage (315) which is a vola...
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WO/2005/076123A1 |
A differential clock-pulse compensation between the clock-pulse system (23) of a digital line-connected data interface and the asynchronous clock-pulse system (22) of a digital wireless data interface is carried out, whereby a variable (...
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WO/2005/069121A1 |
An asynchronously operated FIFO pipe-line (10a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a value of the data item. The FIFO pipelines (1...
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WO/2005/066827A2 |
A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence tha...
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WO/2005/057861A1 |
A transfer device (20) includes: means for generating a bit string (13) in which a bit string (14q) is arranged in a predetermined order by performing only logic operation without subjecting the bit string (14q) received from an I/O devi...
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WO/2005/039122A1 |
The invention relates to a method and equipment for controlling the congestion management and transmission-link-capacity scheduling in packet-switched telecommunications, in such a way that 1) it is possible to define what share of the c...
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WO/2005/039123A1 |
The invention relates to a method and equipment for performing aggregate-portion-specific flow shaping in packet-switched telecommunications, in such a way that the traffic flows (V1-VL) arriving in the system can be arbitrarily bundled ...
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WO/2005/029342A1 |
A method of reconciling a first data structure with a second data structure that is a subsequently modified version of the first data structure. Initially, each node in the first data structure for which a change has been made to a corre...
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WO/2005/024624A1 |
A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses with a second clock rate. The memory can ...
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WO/2005/024542A2 |
The invention relates to a digital signal processing device comprising: input storage means (3; 5); a computational device (4) that is connected to said means, defines a data path (9) and contains at least one arithmetic unit (6) in addi...
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WO/2005/020062A1 |
There is described a dynamic memory buffer (30, 210) for buffering between one or more software applications (40) executing on computing means and one or more data generating and/or receiving devices (20) in communication through the buf...
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WO/2005/013639A2 |
The buffer management system (100) is arranged to control in a data communication system an end to end delay (&Dgr ) of a data unit (150) from input to output. Blocks (104, 106) of data units (150, 152) are written in a buffer (102) with...
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WO/2005/008472A1 |
A method for buffering variable length data at a decoupler (110) includes receiving, at a decoupler (110), a request to queue variable length data from a producer (108), with the decoupler comprising a management header (205) and buffer ...
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WO/2005/006177A1 |
Briefly, a re-timing buffer system that may insert or remove dummy data during frequency translation.
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WO/2005/006195A2 |
A system (10) for selectively affecting data flow to and/or from a memory device (16). The system (10) includes a first mechanism (24, 26) for intercepting data bound for the memory device (16) or originating from the memory device (16)....
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WO/2005/003956A1 |
The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing acc...
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WO/2005/003955A2 |
FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operat...
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WO/2004/114166A2 |
Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a sof...
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WO/2004/109523A2 |
An apparatus (100) for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd&lowbar clk (103) is supplied ...
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WO/2004/107198A1 |
Described is a system and method for applying transforms to multi-part files (202). A request is received to access a stream within a multi-part file. Upon receipt of the request, a list of transforms associated with the stream is identi...
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WO/2004/102555A1 |
A method is described for setting a disc speed in a disc drive apparatus (3)which is in data transfer communication (7) with a host system (2), wherein data transfer between carrier and drive apparatus takes place with a carrier/drive tr...
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WO/2004/095460A2 |
The amount of jitter incurred when reading data written into a FIFO (12) can be reduced by clocking the FIFO with Read Clock pulses at a frequency x fn where x is a whole integer and fn is the frequency at which the memory is clocked to ...
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WO/2004/092945A2 |
A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream....
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WO/2004/088486A1 |
A lookup table device adapted to convert a digital input signal into a predetermined digital output signal corresponding to the digital input signal. This device includes a separator information storage unit 10 in which separator informa...
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WO/2004/061644A1 |
An access control method achieves enhanced security and accuracy compared with other systems through recognition of one or more distorted biometrics. The method includes outputting a distorted biometric print from a surface acoustic wave...
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WO/2004/059471A2 |
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first tr...
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WO/2004/053680A2 |
A buffer management system (100) partitions a total memory space (200) into a programmable number of substantially uniform-size buffers (220-223). An application communicates the desired number of buffers to the buffer management system ...
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WO/2004/053707A1 |
A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width (250). Then, a bit width of a second operand associated with a proces...
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WO/2004/051492A1 |
A storage device for compressing the same input value by using an input processing section, a data storage device, a FIFO memory, and an output processing section. The input processing section checks, for the input value, data stored in ...
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WO/2004/044731A2 |
A method and device is provided for performing rotate operations on operands having a size of 2N bits, alternatively, for performing rotate operations on two operands each having a size of N bits to the left, whereby N is an integer. The...
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